Re: CMOS logic, efficiency versus frequency?

From: Jim Thompson (thegreatone_at_example.com)
Date: 02/11/05 

Date: Fri, 11 Feb 2005 07:51:17 -0700

On Fri, 11 Feb 2005 14:31:28 GMT, John Doe
<jdoe@usenet.is.the.real.thing.com> wrote:

>In as many words as possible, someone is apparently trying to tell me
>that CMOS logic becomes abnormally inefficient as operating frequency
>rises, that it's only efficient when idle.
>
>I have designed and built lots of circuits with CMOS logic (thanks to
>National Semiconductor's 1988 CMOS logic data book). The family
>seemed great for micropower devices including oscillators.
>
>My main question is this:
>As operating frequency rises within normal limits, does CMOS become
>grossly inefficient compared to other typical forms of logic like
>maybe TTL? I don't know much about typical logic families.
>
>>From what I recall, the main CMOS power consumption problem occurs
>when inputs rise and fall slowly, that it is extremely low power
>during normal operation.
>
>Thank you.

My limited logic experience is that, on-chip, the
efficiency/functionality crossover point from PECL-to-CMOS is at about
250MHz.

                                        ...Jim Thompson 

-- 
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

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