Re: Slight digression Re: Power-On Reset

From: Allan Herriman (allan.herriman.hates.spam_at_ctam.com.au.invalid)
Date: 02/23/05 

Date: Wed, 23 Feb 2005 18:37:06 +1100

On Tue, 22 Feb 2005 19:29:16 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:

>In article <c1vm119m9fhregkak342gsrdupevesdiq6@4ax.com>,
>Jim Thompson <thegreatone@example.com> wrote:
>[...]
>>The specification requires 1.65V <= VDD <= 5.5V, over process corners
>>and -40°C to +105°C
>>
>>I PASS ;-)
>
>Many FPGA and CPLD circuits do not become sane until the supply voltage
>reaches and stays above some voltage. It would be nice if the power on
>reset chips also could be used to force the SELF-DESTRUCT signal to ground
>and the EXPLODE-IN-FLAMES/ signal near Vcc until after the RESET is over
>and then glitch free connect them to the signals from the CPLD.

That reminds me of an 80c552 circuit I designed once. The Philips
data*** quite explictly stated that the port lines would go high
when reset was asserted (and the clock was running!). But, as it
turned out, that only applied while Vcc was within tolerance. When
Vcc fell to about 2V or so, the outputs would go low, causing all
sorts of mayhem.

I fixed it by gating the port outputs with a 74HC part.

Regards,
Allan

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