Re: 2 pulses from 1

From: Fred Bartoli (fred._canxxxel_this_bartoli_at_RemoveThatAlso_free.fr_AndThisToo)
Date: 03/09/05


Date: Wed, 9 Mar 2005 14:02:29 +0100


"Terry Pinnell" <terrypinDELETE@THESEdial.pipex.com> a écrit dans le message
de news:ivnt219o2uqv0aui047q2h3p9vkcu6d111@4ax.com...
> This morning I breadboarded both Fred Bloggs' final circuit
> news:4224845A.6080401@nospam.com and Fred Bartoli's. Both work fine
> thanks.
>
> The latter is especially attractive because of its delightfully low
> component count, as well as its novelty. My test input was a clean
> square wave from a function generator, so of course the circuit might
> need a front-end clean-up in practice. However, the outputs would
> probably be fine without further squaring up, as their leading edges
> were fast.
>
> But how does it work please?! What function does that left hand PNP
> serve, with its gate permanently at Vdd?
>

Hi Terry,
don't forget its emitter :-)

There are 3 basic circuits to build around a BJT : common emitter, common
base and common collector (emitter follower).
Google for those and you'll find all the needed information.

As you've seen, there are 2 transistors, the right one in common emitter
configuration, the left one in common base.

                     10K
                     ___
                  .-|___|-+------+-----VDD
                  | | |
        1K 1n | | |
 12V ___ || | A | |<
>-|___|--||--+-------|----| Q2
 pulse || | | |\
                  | | |
>| | |
               Q1 |-----' |
                   /| |
                  | |
        Set <-----+ +-----> Reset
                  | |
                 .-. .-.
                 | | | |
             R1 | | | | R2
                 '-' '-'
                  | |
                  | |
                 === ===
                 GND GND

Due to the base emitter junctions, the A point is clamped to +/- 0.6V around
VDD.
On rising edge, Q2 is reverse biased and the capacitor current is injected
into Q1 emitter => positive pulse on the set output.
On falling edge Q1 is reverse biased and the capacitor current turns Q2 on
=> positive pulse on the reset output.

The 1K resistor obviously limits injected current.
R1 needs to be > 1K*VDD/(12-VDD-0.6).

BTW, since those transistors drive a regenerative circuit (your NOR SR
latch) you don't need squaring after the transistors: the hysteresis is
built into the SR latch.

-- 
Thanks,
Fred.


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