Re: Current source design (tricky?)

From: Fred Bloggs (nospam_at_nospam.com)
Date: 03/12/05 

Date: Sat, 12 Mar 2005 22:00:44 GMT

Larry Brasfield wrote:
> "Fred Bloggs" <nospam@nospam.com> wrote in message
> news:42334D1C.8070303@nospam.com...
>
>>
>>Larry Brasfield wrote:
>>
>>>"Fred Bloggs" <nospam@nospam.com> wrote in
>>> message news:4232DFB9.3020107@nospam.com...
>>>
>>>
>>>>Larry Brasfield wrote:
>>>>
>>>>
>>>>>"Terry Given" <my_name@ieee.org> wrote in message
>>>>>news:qypYd.8841$1S4.942601@news.xtra.co.nz...
>>>>>
>>>>>
>>>>>>Larry Brasfield wrote:
>>>>>
>>>>>...
>>>>>
>>>>>
>>>>>>>A number of op-amps on the market today are
>>>>>>>very tolerant of capacitive loading because they
>>>>>>>have a feature whereby that loading causes the
>>>>>>>gain-bandwidth of the part to drop, almost in
>>>>>>>proportion to the loading, such that the extra
>>>>>>>pole remains far enough above the unity gain
>>>>>>>crossover frequency that stability is preserved.
>>>>>>>The LM8261 suggested by Mr. Hill is a good
>>>>>>>example of this class.
>>>>>>
>>>>>>I have been bitten quite badly by a similar "feature" in
>>>>>>the LM6134 (its a slew-rate modification).
>>>>>
>>>>>The feature I mentioned above works by causing the
>>>>>effective value of an internal capacitance to increase.
>>>>>So it changes both the linear small-signal response
>>>>>(less GBW) and the slew limiting (slower).
>>>>
>>>>Nah- you're full-o-shyte! The capacitive loading decreases the effective internal capacitance due to Miller effects because it
>>>>reduces the gain.
>>>
>>>
>>>You are the one who is full of it, Fred.
>>>
>>>The way the feature works, typically, is by means of
>>>a capacitor placed between the output and the "gain
>>>node", the internal node where current sources develop
>>>the device's voltage gain. The output buffer, under light
>>>load conditions, bootstraps this capacitor so that it does
>>>not much load the gain node relative to the AC grounded
>>>integrating capacitor. When a capacitive load is present,
>>>the increased drop across the buffer output impedance
>>>increases the current that must be supplied to the "gain
>>>node" for any given dV/dt. This represents an increase
>>>in the effective capacitance loading the "gain node", and
>>>serves to reduce the gain bandwidth while tending to
>>>leave the excess poles unchanged.
>>>
>>>Miller effect has very little to do with it. In fact, Miller
>>>effect, to the small extent it occurs, acts only to slightly
>>>move some internal excess pole(s) out a little bit when
>>>a capacitive load is present.
>>>
>>>You, or at least anybody capable of learning something,
>>>can see a description of this feature's operation and a
>>>schematic in the data*** for Linear Technology's LT1812.
>>>Start at:
>>>http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1154,C1009,C1022,P1838
>>>
>>>[More blather founded on spite and ignorance cut.]
>>>...
>>>
>>>
>>>>who has never built anything in his life.
>>>
>>>
>>>Your ability to discern such a falsehood from such a
>>>distance with so little evidence marks you.
>>>
>>
>>That's not what the LM8261 is doing- it is Miller effect on two CE output transistors- and that is the OA you mentioned.
>
>
>
> You are exhibiting poor reading skills here, Fred.
>
> What I described above, before another poster
> ever mentioned the LM8261, is indeed different
> from what the LM8261 does. I never claimed
> that the LM8261 acts as I describe above, and,
> in fact, I expressly denied in this very thread that
> the LM8261 acts per the above.
>
> As for the LM8261 relying on Miller effect, you
> clearly do not understand the large-signal behavior
> that is clearly evident from both the description and
> schematic published in the LM8261 data***. To
> review, (for the benefit of those who are not pig-
> headed), Miller effect occurs when a voltage gain
> stage has capacitive feedback into its input, and
> occurs under small signal conditions as well as
> large signal conditions. The "capacitive load
> accomadation" feature described for the LM8261
> is strictly limited to large signal conditions. So,
> how one might confuse it for Miller effect is a
> puzzle. Care to explain that, Fred? Perhaps you
> should limit your intellectual exertions to the name
> calling that you have practised so diligently.
>

You think you're smart- but you come across as an ignorant little parrot
and pseudo-intellectual. Go back and read the LM8261 data***- it is in
fact the Miller effect that is exploited to achieve the gain and phase
margin with capacitive loading- and it works exactly the opposite of
your bs explanation by moving the internal dominant pole to a higher
frequency and not a lower frequency. Like most phony little piss-ant
weakling USENT frauds, you like to insinuate all this depth of
understanding, but it will be a cold day in hell before we see any
circuits or analysis coming out of that ass-hole you call a mouth. Your
little junior high school level algebra on that summing amplifier is a
case in point- really weak stuff. Here are your exact words where you
state the LM8261 is an example of a class of OA's that drop their GBW-
which is clearly wrong:

"A number of op-amps on the market today are
very tolerant of capacitive loading because they
have a feature whereby that loading causes the
gain-bandwidth of the part to drop, almost in
proportion to the loading, such that the extra
pole remains far enough above the unity gain
crossover frequency that stability is preserved.
The LM8261 suggested by Mr. Hill is a good
example of this class.

Adding a load isolation resistor to the output
tends to defeat that feature, so I would not
add it unless using an op-amp without that
bandwidth reduction feature."

As usual with NG trolls- you just want to talk and talk and talk and
talk....you will never produce anything substantial- at least you're
consistent with the rest of your life.