Re: Problem with Spice - it won't allow me to change bounds of graph

"Larry Brasfield" <donotspam_larry_brasfield@xxxxxxxxxxx> wrote in
news:VAZ2e.37$oI2.968@xxxxxxxxxxxxxxx:

> You PWL spec presents a ramp as the setpoint
> for the amplifier to follow. This is not what people
> usually use to explore response time. (It can be,
> for some systems, but just not often compared to
> step response.)

I understand that - I just wanted to be sure I was getting a linear
(though delayed) output.


> I observed similar behavior. The circuit appears to
> have DC convergence problems in the transient
> simulation and AC simulation, so I've attributed
> that strange starting behavior to that issue without
> studying it closely. I trust the simulator's result
> once the transient simulation settles at a believable
> operating point. I take that as occuring after the
> strange, unrequested initial flailing ceases.

I already have all the components needed (well, different FETs, but
similar enough that I think they will work) sitting around the lab
anyways, so I'm going to see how it performs in the real world. If I get
similar results, is there any way to modify this circuit so as to
improve response time? I looked back at my original post from two weeks
ago and couldn't find anything along those lines, though it's possible
that I missed something due to the very large size of that topic (over
150 posts! eek)

> I would suggest an input like this:
> PWL(0, 0.1, 40m, 0.1, 40.05m, 10, 200m, 10)
> to see your step response past the time taken for
> the true initial conditions to be achieved.

We think alike - That's almost exactly how I found a response time of
30ms

-Michael
.

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