Re: PFD for John Larkin

On Sun, 03 Apr 2005 12:24:51 -0700, Jim Thompson
<thegreatone@xxxxxxxxxxx> wrote:

>John, See...
>
>Newsgroups: alt.binaries.schematics.electronic
>Subject: In Reply to a PFD Question on S.E.D - DD-PFD.pdf
>Message-ID: <5ig051ttsfj97dfkvgruj0kq4oasqobm5a@xxxxxxx>
>
> ...Jim Thompson


Most cool. Thanks. This will implement in one or two Xilinx CLBs, with
around 100 ps max prop delay. Looks like the pumpup and pumpdown can
overlap a bit, which is good.

Interesting: if the fpga logic is too fast, the overlap may go away
because the tristate charge-pump outputs can't respond fast enough to
very skinny pump pulses. Dunno, will consider. One could always add a
little delay into the ff resets path, I guess, or place the r-s latch
far away from the flipflops on the chip.

We may need to be careful that the compiler doesn't "improve" it for
us.

John

.