Re: simple frequecny multiplier

"John Larkin" <jjSNIPlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in
message news:qve95150hjeho69si4nqn7raqsvtn2qqg9@xxxxxxxxxx
> Why are picosecond delays interesting here?
> What's the application?

its for an experiment trying detect any relative change in speed of light.

> 1 ps RMS jitter over 100 ms time will be very difficult. A good
> crystal oscillator can do a few tens of ps over 100 ms; a very good
> ocxo can hit 1 ps over that time.

im using the latest VCTCXO from cmac cfpt-9000 series wich are suposed to be
very good, certainly from stability anyway although they dont quote phase
noise/jitter explicitly, i think its suposed to be one of the lowest,
certainly stability is very good. maybe better over short term than an ocxo
as it operates at lower temperature and has no thermal feedback loop. i
beleive you can also now get these as a oven controled version too. its
useful to know the figures you mentioned tho.

i think it might be posible, even if it means integrating over many cycles,
although this isnt something i have planed for at this stage.

> Any following circuitry must be very
> good to not add picoseconds of jitter.
> If you're trying to characterize the phase change of a 40 MHz signal,
> multipling may not make things better and could well make things a lot
> worse. Measuring anything analog to one part in 25,000 will always be
> tricky.


yes wich is why i was reluctant to go with a PLL i assumed a humble
multiplier wouldnt add much jitter at all over 100ms. the voltage output
from the phase detector would be very small at 40mhz and hence suceptable to
noise at that point. maybe a more moderate multiplaction of x3/x5 that i can
easily acheive now would be more optimal, il probably try that for now but
leave room for the x25 circuit, or maybe try x3 x3.

there realy isnt a lot of circuitry between the frequency generators and the
phase comparator, heck there isnt actualy any ! wel apart from a length of
coax/trasnmison line wich i hope isnt going to misbehave. the phase
comparator would be a gilbert cell aranged to give a null output on matching
phase i think its aranged like this .. (A-B) X J(A+B). the two clocks would
be synchronized within a PLL with an exceedingly long response time so as
not to cancel out the result.

Colin =^.^=


.

Quantcast