Re: Cirrus Logic DAC requirements

An update to my last post, I have been advised on how I can meet the
sample frequency, by setting the CPU's MCK master clock divisor
registers, which reaches the memory controller and the embedded CPU
peripherals (SSC).

The sample (LRCK) frequency can be flexible, say 44.1kHz or 48kHz, when
further divided in the SSC from the MCK, but there doesn't seem to be
any way of outputting a (256x or 384x faster) clock out from the
processor, as I can't find a way to route this MCK signal out to my
DAC.

and Pooh bear you are right, it does need to be synchrnously derived,
it is that which I need.

In short, the DAC needs:

256x:
LRCK = 48kHz | 44.1kHz (LRCK is sample frequency)
MCLK (12.288MHz) | (11.2896MHz)

or 384x:
LRCK = 48kHz | 44.1kHz (LRCK is sample frequency)
MCLK (18.4320MHz) | (16.9344MHz)

I have the I2S controller, but not the MCLK for the DAC!

.