Re: PWM Amp Design

"Larry Brasfield" <donotspam_larry_brasfield@xxxxxxxxxxx>
wrote in message news:pwT5e.13$AV3.440@xxxxxxxxxxxxxxxxxx
> "Chris Carlen" <crobc@xxxxxxxxxxxxxxxxxxxxxxxx> wrote
> in message news:d38qfa02aif@xxxxxxxxxxxxxxxxxxxx
....
>> My idea was that since I had to build an amp for about 3.5A RMS into the load of 2.5ohm+250uH
....

[re phase delay up to 150 Hz]
>> 2 degrees.
>
> I suppose I can translate that to flat delay within +/- 37 uS
> from DC to 150 Hz and beyond that, don't care.
....
>>> Is it a 2 pole LC LPF, nominally?
>>
>> Yes.
....
>>>> My present load will be a 2.5 ohm coil with 250uH of inductance.
>>>> Thus the LC filter elements are 22.5uH and 7.2uF.
....
> May I presume you are willing to use a 10% ceramic
> cap and 5% gapped core set for the inductor? (This
> may well be relaxed once the phase delay performance
> is simulated or analyzed with respect to sensitivity.)

The design is not very sensitive considering the fairly
wide group delay band that is apparently allowed.
The above accuracy is likely to be excessive.

....
> Having sketched a quick root-locus for this, I
> am still convinced. I have two complex poles
> in G, near the imaginary axis, and two zeros in
> H near the real axis and about as far from the
> origin as the LPF poles. (And some poles way
> to the left to make it realizable.) With the right
> loop gain, the poles move to the left and around
> the zero pair, ending up just about wherever they
> are most useful for that controlled delay filter I
> mentioned.
>
> What kind of DC accuracy do you need? Can
> gain variation induced by 80V supply variation
> be handled by an outer loop? Or does this power
> amp have to have very tight gain and offset specs?
> (Until it appears necessary, I hesitate to add a pole
> at zero just to reduce maybe tolerable error.)

Upon further reflection, an integrator in the forward
path to get precise gain and offset is no big deal.
With a little tweaking to get the 3 poles properly
related to each other, the group delay easily falls
within a couple uS band out to 400 Hz. With even
more effort, (ajusting the zero positions and care
in setting loop gain), the 3 poles could be made to
conform to a cookbook equiripple group delay LPF.
>From the initial results of simulation, I see no need
to bother with that mathematical exercise.

....
>> They will be designed to hold up at least 75% of their inductance to 10A.
>
> Gapped parts would do better. If the open-loop
> response can be kept more predictable, it will be
> easier to control the close-loop phase delay. The
> LC poles do not have to be kept so far out.

For the simulation included below, I set the LC poles
about 10 times closer to the origin, similar damping.
This should take down the ripple most of 40 dB. It
can work to set the filter higher, but the shifted poles
get closer to the switching frequency than I would
like to see.

>> So far I haven't dealt with any cases of having complex poles in the open loop, so this is virgin territory.
>
> That's were it becomes fun. With a few more
> answers, I am inclined to simulate a controller
> and idealization of your plant.

Following is source for an LTSPice simulation
(see http://www.linear.com/company/software.jsp )
with the 2 zeroes and 1 pole in H, and 1 pole
at 0) in G. This is not any kind of final design,
but it does demonstrate how easy it will be to
attain the performance so far mentioned. For
a real circuit, there may need to be a bit more
filtering to keep switching junk out of the first
near-differentiator (or it may be fine as is). It
will certainly work to use slower op-amps.

========== begin lcyank.asc ==============
Version 4
*** 1 880 740
WIRE -528 496 -528 448
WIRE -512 240 -512 224
WIRE -512 336 -512 320
WIRE -496 448 -528 448
WIRE -496 528 -496 448
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FLAG -512 336 0
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FLAG -368 448 VP
FLAG -208 304 VP
FLAG -32 464 VP
FLAG -368 528 VN
FLAG -32 528 VN
FLAG -208 368 VN
FLAG -432 224 VS
FLAG 192 176 VX
FLAG 16 176 VA
FLAG -96 336 VC
FLAG -432 336 0
FLAG 32 544 0
SYMBOL res 240 288 R0
SYMATTR InstName R1
SYMATTR Value 2.5
SYMBOL ind 240 176 R0
SYMATTR InstName L1
SYMATTR Value 250?
SYMBOL cap 144 240 R0
WINDOW 0 7 -9 Right 0
WINDOW 3 -7 24 Right 0
SYMATTR InstName C1
SYMATTR Value {7.2?/LPFS}
SYMBOL ind 32 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName L2
SYMATTR Value {22.5?/LPFS}
SYMBOL Opamps\\LT1215 -32 432 M0
SYMATTR InstName U1
SYMBOL Opamps\\LT1215 -208 272 R0
SYMATTR InstName U2
SYMBOL bv -32 176 R0
WINDOW 3 30 -75 Left 0
SYMATTR InstName B1
SYMATTR Value V={GX*V(VC)}
SYMBOL voltage -512 224 R0
WINDOW 123 -25 94 Right 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMATTR Value2 AC 1
SYMBOL voltage -384 448 R90
WINDOW 0 -14 103 VBottom 0
WINDOW 3 4 10 VTop 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL voltage -496 528 R270
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WINDOW 3 -4 100 VBottom 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL res -448 224 R0
SYMATTR InstName R2
SYMATTR Value 12k
SYMBOL cap 144 496 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL res 160 368 R90
WINDOW 0 -4 71 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value 12k
SYMBOL res 16 368 R90
WINDOW 0 11 19 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 12k
SYMBOL cap -160 240 M270
WINDOW 0 23 7 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C3
SYMATTR Value 1n
SYMBOL res -352 208 M90
WINDOW 0 -3 73 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 12k
SYMBOL res 128 464 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R6
SYMATTR Value 1k
TEXT -204 606 Left 0 !.ac oct 20 10 500k
TEXT -496 96 Left 0 !.step param GX 0 5 1
TEXT -496 128 Left 0 !.param LPFS=.1
========== end lcyank.asc ==============

The above simulation should be a convincing demonstration
that using the controller to get the PWM filtered output
response apparently desired by the OP is feasable and
unlikely to present serious problems. Obviously, gains
and maybe offsets will need adjustment once the VCVS
is replaced by the PWM IC. When current limiting is put
into place, some attention to limiting in the controller will
be in order. A sensitivity analysis for L and C variation
would be smart. It might be a good idea to make sure
no limit cycles are possible, using time domain simulation
and a range of step inputs.

--
--Larry Brasfield
email: donotspam_larry_brasfield@xxxxxxxxxxx
Above views may belong only to me.


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