Re: PWM Amp Design


Chris Carlen wrote:

> [For] academic purposes I am still curious about what other
> approaches other than an equalizing network one might try to solve
> the reactance problem? It seems to me that one approach might be
> to try to sense the PWM output post-filter, and then compensate
> for the peaking within the PWM amplifier control loop.

Here's an example of a self oscillating class d amplifier 'a la the
leapfrog method that both contains the output filter within its
feedback loop and provides integral output current limiting:

http://groups.yahoo.com/group/LTspice/files/adventures%20with%20analog/class%20d%20audio/ClassD_LeapFrog_UcD.asc

~~~~ ClassD_LeapFrog_UcD.asc (cut&paste & mind the word wrap) ~~~~
Version 4
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WINDOW 3 51 32 Left 0
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WINDOW 3 32 48 Left 0
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WINDOW 3 36 40 Left 0
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WINDOW 3 32 48 Left 0
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SYMATTR Value 3k3
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WINDOW 3 32 56 VTop 0
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WINDOW 3 32 56 VTop 0
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WINDOW 3 0 56 VBottom 0
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WINDOW 3 32 56 VTop 0
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SYMATTR SpiceLine ""
SYMATTR SpiceLine2 ""
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WINDOW 3 0 96 Left 0
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SYMATTR SpiceLine ""
SYMATTR SpiceLine2 ""
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SYMATTR InstName Ro
SYMATTR Value {Ro}
TEXT -1168 688 Left 0 !.tran 0 225u 25u uic
TEXT -120 672 Left 0 !.model STP14NF12 vdmos (Rg=5 Rd=90m Rs=70m Vto=3.5 Kp=3\n+ Cgdmax=200p Cgdmin=20p Cgs=420p Cjo=60p Is=10p Rb=140m)
TEXT -1168 312 Left 0 !.model limit d(Ron=1u Vfwd=5 Vrev=5)
TEXT -1168 352 Left 0 !.subckt opamp 1 2 3\nG1 0 3 2 1 10k\nC1 3 0 160µ Rpar=100\nD1 3 0 lim\n.model lim d(Ron=1u Vfwd=12 Vrev=12)\n.ends opamp
TEXT -1168 648 Left 0 !.step param Ro list 1G 6 1u
TEXT -1168 624 Left 0 !.param a=5 Ro=6
TEXT -384 -312 Center 0 ;UcD180 Class D Amplifier Power Stage \ndriven by LeapFrog control\nby analogspiceman, March, 2005
TEXT -1168 528 Left 0 ;10kHz square wave response into\nopen, nominal, and short circuits.\nPlot V(o) and I(L1)
.

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