Re: PWM Amp Design

"Chris Carlen" <crobc@xxxxxxxxxxxxxxxxxxxxxxxx> wrote
in message news:d38qfa02aif@xxxxxxxxxxxxxxxxxxxx

> I need to spend some more time with pencil and paper to understand
> how the controller can "move the poles" of the filter.

The LTSpice simulation I posted Sunday, with suitable
corrections for some posting anomalies, can be used
to show how the poles move versus loop gain and see
the range of loop responses available.

Below, (after posting, I hope), is a revised form of the
same controller with a pair of solutions selected by NS.
(Loop gain GX, LPF scaling LPFS, and scaling of the
zero pair and realization pole, ZW, are all set by NS.)
I've set it up so that the controller response can also be
scaled (approximately, ignoring op-amp poles), not just
the LC LPF. This makes it more convenient to simulate
for the output filter you may want to actually build. As
you can see, it is quite possible to move the LPF poles
closer to the origin as I have suggested.

The group delay is (about) either 33uS or 50uS and
flat within a few hundred nS out to 400 Hz. You might
note that, after shifting by the controller, the response is
close to what your bare LC LPF was doing.

========== begin lcyanka.asc =============
Version 4
*** 1 880 740
WIRE -528 496 -528 448
WIRE -512 240 -512 224
WIRE -512 336 -512 320
WIRE -496 448 -528 448
WIRE -496 528 -496 448
WIRE -480 448 -496 448
WIRE -480 528 -496 528
WIRE -432 224 -512 224
WIRE -368 224 -432 224
WIRE -368 448 -400 448
WIRE -368 528 -400 528
WIRE -352 448 -368 448
WIRE -352 528 -368 528
WIRE -256 224 -288 224
WIRE -256 320 -256 224
WIRE -256 400 -256 352
WIRE -256 496 -256 480
WIRE -240 320 -256 320
WIRE -240 352 -256 352
WIRE -224 224 -256 224
WIRE -144 224 -160 224
WIRE -144 336 -176 336
WIRE -144 336 -144 224
WIRE -128 496 -256 496
WIRE -128 496 -128 384
WIRE -96 336 -144 336
WIRE -80 336 -96 336
WIRE -80 384 -128 384
WIRE -64 496 -128 496
WIRE -32 208 -32 192
WIRE -32 304 -32 288
WIRE 16 192 -32 192
WIRE 16 384 0 384
WIRE 16 480 0 480
WIRE 16 480 16 384
WIRE 32 512 0 512
WIRE 32 544 32 512
WIRE 48 192 16 192
WIRE 48 544 32 544
WIRE 64 384 16 384
WIRE 80 480 16 480
WIRE 144 544 128 544
WIRE 144 560 144 544
WIRE 160 192 128 192
WIRE 160 224 160 192
WIRE 160 304 160 288
WIRE 192 192 160 192
WIRE 208 192 192 192
WIRE 208 384 144 384
WIRE 208 384 208 192
WIRE 208 416 208 384
WIRE 208 480 160 480
WIRE 256 192 208 192
WIRE 256 208 256 192
WIRE 256 304 256 288
WIRE 256 400 256 384
FLAG -512 336 0
FLAG -32 304 0
FLAG 256 400 0
FLAG 160 304 0
FLAG -528 496 0
FLAG -368 448 VP
FLAG -208 304 VP
FLAG -32 464 VP
FLAG -368 528 VN
FLAG -32 528 VN
FLAG -208 368 VN
FLAG -432 224 VS
FLAG 192 192 VX
FLAG 16 192 VA
FLAG -96 336 VC
FLAG 144 560 0
SYMBOL res 240 288 R0
SYMATTR InstName R1
SYMATTR Value 2.5
SYMBOL ind 240 192 R0
SYMATTR InstName L1
SYMATTR Value 0m25
SYMBOL cap 144 224 R0
WINDOW 0 -8 29 Right 0
WINDOW 3 5 59 Right 0
SYMATTR InstName C1
SYMATTR Value {7u2/LPFS}
SYMBOL ind 32 208 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 4 45 VBottom 0
SYMATTR InstName L2
SYMATTR Value {22u5/LPFS}
SYMBOL bv -32 192 R0
WINDOW 0 -28 19 Right 0
WINDOW 3 362 -57 Right 0
SYMATTR InstName B1
SYMATTR Value V={if(abs(GX*V(VC))>30, 30*sgn(V(VC)), GX*V(VC))}
SYMBOL voltage -512 224 R0
WINDOW 3 -56 151 Left 0
WINDOW 123 21 95 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1m 0 1.01m 1 2m 1)
SYMATTR Value2 AC 1
SYMBOL voltage -384 448 R90
WINDOW 0 -14 103 VBottom 0
WINDOW 3 4 10 VTop 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL voltage -496 528 R270
WINDOW 0 -32 10 VTop 0
WINDOW 3 -4 100 VBottom 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL cap 224 480 R180
WINDOW 0 -7 37 Right 0
WINDOW 3 -6 9 Right 0
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL res 160 368 R90
WINDOW 0 -5 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value {rz}
SYMBOL res 16 368 R90
WINDOW 0 -6 49 VBottom 0
WINDOW 3 33 90 VTop 0
SYMATTR InstName R4
SYMATTR Value {rz}
SYMBOL cap -160 240 M270
WINDOW 0 23 7 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C3
SYMATTR Value 1n
SYMBOL res -384 208 M90
WINDOW 0 -3 73 VBottom 0
WINDOW 3 35 63 VTop 0
SYMATTR InstName R5
SYMATTR Value {rz}
SYMBOL res 176 464 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 34 8 VTop 0
SYMATTR InstName R2
SYMATTR Value {rz/pzr}
SYMBOL res -240 384 M0
WINDOW 0 39 51 Left 0
WINDOW 3 31 90 Left 0
SYMATTR InstName R6
SYMATTR Value {rz}
SYMBOL res 144 528 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R7
SYMATTR Value {rz/2}
SYMBOL Opamps\\LT1215 -32 432 M0
SYMATTR InstName U1
SYMBOL Opamps\\LT1215 -208 272 R0
SYMATTR InstName U2
TEXT -204 606 Left 0 !.tran 0 2m 0 1u
TEXT -496 40 Left 0 !.param GX={table(NS,1,125,2,75)}
TEXT -496 72 Left 0 !.param LPFS={table(NS,1,0.1,2,0.25)}
TEXT -496 104 Left 0 !.param ZW={table(NS,1,40k,2,60k)}, pzr=10
TEXT -104 8 Left 0 ;For LPFS=1, L2.C2 poles at +/- j * 78.6K r/S
TEXT -496 160 Left 0 !.param rz={1/(1n*ZW)}
TEXT -496 8 Left 0 !.step param NS list 1 2
TEXT -288 -40 Left 0 ;Control of Single-Stage LC LPF
========== end lcyanka.asc =============

There are a number of steps remaining between the above
and a real circuit. The scaling between the controller and
the PWM does not reflect your 80V output range. There
should be some careful attention given to limiting behavior
because the loop is not stable for a range of lower loop
gain values. (The LC poles move into the RHP and back
into the LHP as loop gain is increased from 0.) This means
that limiting in an unfortunate location could serve to reduce
the loop gain and permit what is known as a limit cycle
oscillation. It may also be necessary to introduce some
additional low pass filtering to keep the chop frequency
from appearing too much at the output of the controller.

--
--Larry Brasfield
email: donotspam_larry_brasfield@xxxxxxxxxxx
Above views may belong only to me.


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