Re: A strange problem with CMOS Up/Down counter
- From: "Anthony Fremont" <spam@xxxxxxxxxxxx>
- Date: Mon, 25 Apr 2005 07:58:35 GMT
"csl" <csl.parts@xxxxxxxxxxx> wrote in message
<snip>
> I can't seem to figure out what's the problem. It only happens when
one
> returns from 3 to 2 and making an attempting back to 3.
>
> If you have any suggestion, please post. Thanks for reading.
What are you using for the clock signal? If you have pull-ups on the
clock line, how big are they? I've had strange results like this when
the rise time was too slow on the clock.
.
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