Re: Can somebody take a look at this circuit for me?



On Thu, 12 May 2005 21:18:07 +0000, Michael Noone wrote:

> Pooh Bear <rabbitsfriendsandrelations@xxxxxxxxxxx> wrote in
> news:4282E7DF.FCF30727@xxxxxxxxxxx:
>
>> Are you really sure that your active load ( U$2 ) is meant to be
>> configured like that ?
>>
>> Oh - it's just the way you drew it that's confusing. How *do* you
>> generate such odd component references btw ?
>
> What do you mean odd component references? The names are all auto generated
> by Eagle.
>
>> It's quite likely unstable. Try using sensible feedback Rs for
>> starters like 1M ( watch the wattage ) and 1k
>
> The size of the resistors used in the voltage divider circuit will affect
> the performance of the circuit? I chose those high values as I figured
> they'd be fairly easy to obtain and not consume much power - but I
> definitely can change to a smaller set of resistors if needed.
>
>> You can protect the op-amp by adding clamp diodes to its supply rails
>> btw.
>>
>> Graham
>
> Can you elaborate on this? I'm afraid I'm not familiar with the term "clamp
> diode" - and googling it turned up many results relating to things like
> relays, (where I am familiar with the use of diodes to dissipate the
> inductive energy stored in the coil).
>

You would put the diode between the pin you want to protect, and the
positive supply rail in such a way that it is normally reverse biased.
Only if the voltage at the protected pin goes above the supply Voltage
does the diode experience forward bias. Is that clear enough?

Something like this: (Use courier or other fixed-width font for ASCII art
schematic)


VCC
|
+-----+
| |
| --- clamp
| / \ diode
|\ | -----
| \| |
| \ |
| \----+------> To dangerous load
| / |
| / --- clamp
| /| / \ diode
|/ | -----
| |
+-----+
|
GND

> Thanks!
>
> -Michael

In your circuit, you might want to protect the non-inverting input pin and
or the output pin.

I agree with the others who say that the upper FET definitely needs Zener
protection. Might as well add it for the lower one, too. You would use
maybe a 10 V Zener in such a way that it Zeners when Vgs is > 10 V.

Like this: (Use courier or other fixed-width font)


1kV
----
|
---+ Drain
||
gate ---+---|| N-channel MOSFET
| ||
~ ----+ Source
Zener / \ |
diode ----- |
| |
+--------+------- Vout


I also have to point out that you are operating a 1000 Volt transistor
with, potentially, 1000 Volts across it. Normally, I would not
recommend designing with zero margin.

--Mac

.



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