Re: Run SDRAM with slower speed

On Sun, 12 Jun 2005 12:51:12 -0700, "Richard H." <rh86@xxxxxxx> wrote:

>Mike Harrison wrote:
>> This is clear from the datasheets, but one thing that was not at all clear when I was looking at
>> this is how the length of a self-refresh cycle scales at lower clocks. e.g. the Micron MT48LCccMxA2
>> series data fig.37, the time taken for auto-refresh is shown as min 66ns for the -75 speed grade
>> based on 10ns clock, but it does not indicate how many (if any) clocks are required at lower
>> frequencies.
>>
>> This is an issue for design I'll be doing soon & I'd be interested if anyone has any info on this.
>
>I'm currently working on a similar design with the MT48LC series, and
>self-refresh is a key feature. Bit-banging with a slower MCU, it's
>critical to keep from burning a lot of cycles doing refreshes.
>
>According to the datasheet I've got (pg.13), "The Self Refresh command
>can be used to retain data in the SDRAM, even if the rest of the system
>is powered down. When in the self refresh mode, the SDRAM retains data
>without external clocking. ... all the inputs to the SDRAM become Don't
>Care..." This is reinforced by the Self Refresh timing diagrams (p.40).
>
>
>To the OP's question - it'll depend on what kind of SDRAM you're using.
> SDR SDRAM appears to support very slow clocks. OTOH, DDR and above
>have minimum clock speeds, virtually requiring a DRAM controller (which
>these days is hard to find as a separate part.
>
>Richard

Sorry I meant auto-refresh, not self-refresh....

.

Relevant Pages

  • Re: Windows CE 4.2 scheduling
    ... Depending on the CPU. ... bring the SDRAM out of self refresh except via a reset. ... to schedule as every thread is blocked waiting on something (typically I/O ...
    (microsoft.public.windowsce.platbuilder)
  • Re: power management on embedded linux?
    ... processors, typically the SDRAM is put into self refresh, and the ... you take the SDRAM out of self ... the kernel can typically handle it. ... PPC on wake up but its good to here that it works on some platforms so I'm ...
    (comp.os.linux.embedded)
  • Re: Windows CE 4.2 scheduling
    ... it does work on the PXA. ... When there is no access to SDRAM, the memory controller automatically ... transitions it to self refresh. ... I am so focus on the OEMIdle interval but ignore the SDRAM ...
    (microsoft.public.windowsce.platbuilder)
  • Re: Run SDRAM with slower speed
    ... this is how the length of a self-refresh cycle scales at lower clocks. ... According to the datasheet I've got, "The Self Refresh command can be used to retain data in the SDRAM, even if the rest of the system is powered down. ...
    (sci.electronics.design)
  • Re: FIFO in SDRAM
    ... > the read and write operations on that common SDRAM interface. ... > address space on one port as transmit buffer, ... > address space on the other port as receive buffer. ... So in 15 ns he has to send a RAS, wait 2 clocks and then a CAS and a further ...
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