Re: Run SDRAM with slower speed

On Fri, 10 Jun 2005 16:02:19 +0100, Mike Harrison <mike@xxxxxxxxxxxxxxx> wrote:

>On Fri, 10 Jun 2005 09:58:01 -0400, "Tam/WB2TT" <t-tammaru@c0mca$t.net> wrote:
>
>>
>><pbdelete@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
>>news:42a965cd$0$173$cc7c7865@xxxxxxxxxxxxxxx
>>> eeh <eehobbyist@xxxxxxxxxxxx> wrote:
>>>>Hi,
>>>
>>>>Could I run a 150MHz SDRAM with 50MHz clock? Can it still run normally?
>>>
>>> Besides the issue with clock distribution. You must make sure that you
>>> have
>>> sufficient time to refresh all bits.
>>>
>>Might add here that even if you can scale the clock, you can NOT scale the
>>refresh interval.
>
>This is clear from the datasheets, but one thing that was not at all clear when I was looking at
>this is how the length of an auto-refresh cycle scales at lower clocks. e.g. the Micron MT48LCccMxA2
>series data fig.37, the time taken for auto-refresh is shown as min 66ns for the -75 speed grade
>based on 10ns clock, but it does not indicate how many (if any) clocks are required at lower
>frequencies.
>
>This is an issue for design I'll be doing soon & I'd be interested if anyone has any info on this.

Follow-up - I have just had confirmation from Micron that there is no minimum number of clocks
required during the auto-refresh cycle, you just need to meet TRFC, so for example at 25MHz, TRFC
is satisfied after 2 clock periods
.

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