Re: Bizzare behaviour from SG/UC3525

Tony Williams wrote:

> In article <42B8B135.8312B355@xxxxxxxxxxx>,
> Pooh Bear <rabbitsfriendsandrelations@xxxxxxxxxxx> wrote:
> [snip]
> > I then find by accident that if I try to 'provoke' the highside
> > jitter it's affected by my hand capacitance on the switch that I
> > have included to 'stop switching' to the shutdown pin on the
> > 3525. Uh ?
> [snip]
> > I see mismatched timing periods !
>
> > I have OUTA used as the high side drive signal . It looked fine
> > before but it's only 500ns long I discover ! OUTB is 4.5us long (
> > as it should be ) !
>
> I have no experience of smps supplies, just posting
> to register an interest in learning along with you.
>
> Hand capacity effects around the Shutdown input?
> A Shutdown input that is both directly connected to the
> output OR gates, or is capable of doing an early PWM pulse
> termination via the S-R flip flop?
>
> Try sticking a 0.1uF from Shutdown to 0v, right at
> the chip?

Actually I thought 0.1uf was a bit big so I added 10nF there. It had the
desired effect you suggest.

It seemed to stop the 'jitter' on the trailing high side edge but then I
went and switched the damn thing off and the IR2110 went Fizzzz as the
rails decayed ! And it was the the *low* side driver that had gone bad !
It measured 2 ohms form Vs to out after this incident !

My brain is going a bit bonkers.

I'm baffled. Doesn't happen often. Last time I was this perplexed was
when I realised that I had a very fast voltage driver stage in an audio
amplifier that was causing a reverse bias avalanche breakdown problem in
the output devices. And don't even begin to ask how I worked that one
out !

Graham

.

Relevant Pages

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