Re: oscillation in high-voltage MOSFETS connected in series

"Winfield Hill" <hill_a@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in
message news:d9ekuo01idk@xxxxxxxxxxxxxxxxxx
> continued OT from the thread, Looking for pulse-rated zener.
>
> colin wrote...
> > Winfield Hill wrote ...
> >> colin wrote...
> >>> Winfield Hill wrote ...
> >>>
> >>>> This active-zener method works well with low-voltage power MOSFETs,
> >>>> such as under 100V, but it's dangerous with high-voltage FETs, 200V
> >>>> and up, because they have a bad tendency to go into RF oscillation.
> >>>> This is a high-power RF oscillation at frequencies of 15 to 40MHz,
> >>>> which is very difficult to damp with external parts such a ferrite
> >>>> beads, gate resistors, etc. That's because the RF oscillation is
> >>>> internal to the FET, employing its inductance and self capacitance.
> >>>> The required linear properties occur whenever a high current flows
> >>>> while the drain-source voltage is higher than 10 to 20V. The latter
> >>>> condition causes the FET capacitances to drop to the levels where RF
> >>>> amplification is efficient.
> >>>
> >>> If the RF feedback path is wholy internal how would this affect the
> >>> method of using a higher gate drive resistance to slow the current
> >>> fall to limit the voltage to less than the breakdown voltage?
> >>
> >> Two different effects... The slowing of the turnoff means the
> >> coil can flyback and dI/dt discharge as it's doing so, without
> >> reaching the avalanche voltage, if carefully done.
> >>
> >>> or does the zener just add more parasitics to make the difference?
> >>
> >> You're asking if oscillation doesn't happen in the event of a
> >> slowed transition, as in the zener case? It certainly can with
> >> high-voltage MOSFETs, although the dV/dt slewing output helps to
> >> hide it, on the one hand, and perhaps to dampen it, on the other.
> >
> > Yes thanks thats what i was asking, as both cases have the vds>20v
> > at high curent. Trying to think of a way of avoiding it yet still
> > using a more deterministic way of setting the peak voltage.
> >
> > Actually i was wondering if a cascode mosfet arangement would behave
> > any better, again it might make it less noticable as the bottom device
> > would stay more in control of the current, although i would be worried
> > about this as long ago I had some nasty oscilations when i was trying
> > to make a high voltage power supply with several series mosfets (600v
> > mosfets were very limited at the time), but unfortunatly i never had
> > the time (or the experience back then) to get to the bottom of all
> > the diferent modes of oscilations.
>
> Hmm, oscillation for a high-voltage string of MOSFETS in series,
> due to the series connection, you think? As opposed to just the
> bottom MOSFET by itself? How high was the FET operating current
> when you observed oscillation?
>
> Let's evaluate the scene.
>
> For a series-connected MOSFET the current gain is unity from DC
> to a frequency f_T = g_m / 2pi Ciss, where the gate capacitance
> robs the ac signal current away from the FET's source path. For
> a BJT, the transconductance gm = Ic/Vt = 40 Ic. It's lower for
> power MOSFETs, g_m = Id/nVt in the subthreshold region, where
> n = 3 to 5, according to my measurements. So here a MOSFET has
> 3 to 5x lower g_m than a BJT at the same current. Above the
> FET's threshold gate voltage, where the currents are from 5 to
> 100% of the FET's maximum operating current, g_m still rises
> with current, but at a much slower rate.
>
> I would think the bottom line is, you need to work within say
> 20% or higher of the FET's maximum current to get its g_m, and
> thus f_T, high enough to take part in serious RF oscillation.
> While operation at such a high voltage and current is practical
> for a few milliseconds, I imagine it'd create too much power
> dissipation to do continuously.
>
> This means most continuous linear use of power MOSFETs occurs
> in the subthreshold region, where the g_m/Id ratio is higher,
> but where the transistor's f_T remains low, say under 20MHz.
>
> For example, I'm using fqd2n100 surface-mount 2A 1kV FETs in
> a series-connected amplifier. At the maximum current of 4mA
> with 400V across the FET, it dissipates about 1.6W, pushing the
> junction temperature up by about 90C, which is as high as I'm
> comfortable to go. This FET has Ciss = 400pF. At 4mA it has
> g_m = 32mS, which means its f_T = 13MHz. Oops! that's getting
> into a dangerous region. If I was using a similar MOSFET, with
> heatsinks, at currents higher than 4mA, there could be trouble.

Aha I see, it might be that a cascode arangement would be stable.

In my case power disipation was not too much of an issue as the input was
pre regulated with simple scr stage but what was needed specificaly was a
very fast acting short circuit protection. so the output device had to
handle the full voltage at full current only for half a mains cycle or so.

I cant remember the exact layout now but the initial problem I had was that
too much of the transient apeared acros the botom device due to drain-gate
capacitance of the other devices. using a chain of capacitors large enough
meant loading the input/output too much to offer quick enough short circuit
current protection. so i tried to make the transient apear accross each
device as evenly as possible and compensate for any change/diference in
device stats with what seemed a fairly simple chain of resistors capacitors
etc. where I think each gate voltage was derived partly from a divider
between its drain and the lower fets source.

However I think there were too many paths basicaly so I just simply couldnt
understand what was going on and of course as soon as you atach a probe it
all changes, as soon as I got oscilation the things usualy went 'pop' fairly
quickly anyway becuase they all seemed to oscillate wildly and out of phase
and so peaked above their max vds.

I'm fairly sure this wasnt internal oscillation as I added capacitors where
i thought they would do good only to find that it just reduced the frequency
but made it more likly to oscillate. I think the chain of capacitors etc
basicaly formed a signal path in a ring like in a phase shift oscilator but
i just couldnt see it at the time.

I was trying to use much lower voltage fets (200v) as they were far more
robust than the almost available 600v devices but I gues it would of been
better to use a few dozen of those in parallel although I only had 4 at the
time and they were hard to get.

It was basicaly to help trouble shoot a problomatic SMPS/PFC design but that
problem went away first.

The only thing I have come acros that might explain it was a circuit for a
'chaotic oscillator' wich used cascoded fets.

I dare say now i could easily solve the problem with an aditiional 20+ years
experience (and of course easily done with a single fet now) but it was one
of those things you just strongly remember not to tackle anything like that
again lightly.

Its one of those things that makes electronics so chalenging and hard to put
down.

Colin =^.^=


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