Re: need small PAL with SR latch

On Sat, 25 Jun 2005 18:16:56 +0000, colin wrote:

>
> "Keith Williams" <krw@xxxxxxxxxx> wrote in message
> news:MPG.1d25f957cf413709989ae9@xxxxxxxxxxxxxxxxxxxxxx
>> In article <dOVue.4085$BD2.1932@xxxxxxxxxxxxxxxxxxxx>,
>> no.spam.for.me@xxxxxxxxxxxx says...
>> > Hi,
>> > I need a small prgramable logic device with a couple of SR latches,
>> > however they all seem to have D types or other type of latch on the
> macro
>> > cell with a global clock/set/reset, exept for some of the realy big
> ones.
>> >
>> > Ive looked through all of the ones that Farnell sell, and although I
>> > could obviously feed back an output to make an SR latch this wouldnt be
>> > ideal, any one know if there are any like this ?
>> >
>> > Only needs a dozen gates or so to do the job, could do with being
> fast
>> > as posible and in circuit programable etc.
>>
>> The Xilinx SpartanXL had RS latch options in the CLBs, but it wasn't
>> well supported. RS latches tend to cause timing headaches and aren't
>> recommended. If you insist on RS latches the tools will infer one from
>> VHDL, though will bitch loudly (at least Synplify would do both).
>>
>> --
>> Keith
>
> thanks,
>
> Im trying to get to grips with some of the software from the manafacturers,
> I tried Altera's Quartus II and that seems realy nice and easy to use, and
> has no trouble taking my schematic with an rs latch. however they only do
> devices many times larger than what i need. with about 100 too many pins!

Yeow! I have no experience with Altera, but it sounds like you have
something seriously wrong with the setup.

> I tried Lattice and finding this awkward to use but managed to create a
> schematic with an rs latch, I was puzzled becuase I couldnt relate this
> to the data ***, however I realise now this isnt what I need as it is
> using a D type latch (with a clock wich i had ignored), so I reverted to
> using 2 gates to do the RS latch function.

The D-flops often have both Sets and Resets, but often they can't be
connected into the routing matrix, or only one can at a time. You are
asking to do something that the manufacturers try to prevent you from
doing. I had similar problems trying to make a D-type latch. While the
two gates should work, the problem is trying to convince the software that
this really is what you want. It will try to prevent you from doing it.

> Im confused though becuase it seems to have created a gal16v8 but with
> what apears on the chip report to be negative logic outputs wich isnt
> what i asked for or want.

I'm confused. You asked for a 16V8, or it chose for you? You may have
IOB issues as well. Getting the IOB right can be a PITA.

> maybe it would be better to enter it in vhdl ? what would be an ordinary
> rs latch as oposed to a equivalent of a clocked D type latch?

Perhaps something like...
(r,s, and q are standard_logic or standard_ulogic)

SRLatch: Process (S,R) -- Set dominant SR latch
BEGIN
IF s = '1' -- Set is dominant
THEN q <= '1';
ELSE IF r = '1'
THEN q <= '0';
END IF;
END PROCESS;

--
Keith
.

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