Re: need small PAL with SR latch

"keith" <krw@xxxxxxxxxx> wrote in message
news:pan.2005.06.26.18.14.06.823026@xxxxxxxxxxxxx

<big snip >

> Oh, *now* the light goes on. I thought your design came out with 100
> pins. Yes, FPGAs are going to have a lot of pins. ;-)

:D

Its amasing just how many pins some of theses devices have, and with oudles
of gates too and 400mhz clock speed etc, and yet they stil dont consume that
much more power than some of the small ones.

Im realy tempted to try and do something neat to do with all those pins but
cant think of anything right now.

> Not necessarily more idiot-proof, but clocked logic can be simulated
> and timed. Asynchronous logic and loops in logic are nightmares.

Yes its easy to verify setup times are met with clocked logic as everything
just adds up between the edges.

Metastable states in asynch loops can cuase nightmares but they still have
defineable boundries, the latches in the macro cells have internal async
loops hence the setup and min clock width timings inorder to avoid
metastable states but it is much more controled as they will only have 2
adjacent virtualy unloaded gates in the loop.

In logic wich has numerous feedback loops all the possible circular paths
can be very complex and hard to ensure metastable (or race conditon) states
are avoided, but as the theory is reasonably simple a computer should be
able to handle the complexity, but it seems the tools are made to do it the
easy way.

However it seems high speed clocks accross large chips are cuasing problems
and theres interest in using more asycnhrounous techniques such as mixed non
synchronised clock systems however these seem to cuase as much problems, if
you could make a microprocessor internaly completly asynchronous (with of
course suitablly generated handshaking for every movement of data) it would
avoid clock issues altogether.

> You need to know what is in the library though. I try not
> to do this because it messes up the VHDL and makes it less portable. When
> I find it necessary, I keep all such instantiations in seperate files and
> mark them as being technology dependent.

ah yes of course, il have a look to see if there are any asycnhrounous sr
latches already there.

> I found VHDL, at least the synthesizable subset, to be very easy to learn.
> Much of the difficulty is in knowing what synghesis is going to do with
> your source code. Synthesis matches templates, so your job, should you
> choose to accept, ;-) is to learn what templates turn out what logic.

That reminds me of trying to use high level languages in multi tasking
embeded systems.

Colin =^.^=


.

Relevant Pages

  • Re: need small PAL with SR latch
    ... > Its amasing just how many pins some of theses devices have, ... Asynchronous logic and loops in logic are nightmares. ... > Metastable states in asynch loops can cuase nightmares but they still have ... > loops hence the setup and min clock width timings inorder to avoid ...
    (sci.electronics.design)
  • Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred .... Warning. Should I car
    ... 39-   process ... this clock on a dedicated clock routing resource. ... pins I'm using. ...
    (comp.arch.fpga)
  • Re: clock skew problems
    ... The two pins which have a different name are inputs of two BUFGMUX. ... to avoid clock problems and to keep my_clock on the global clock ... it would be fed by standard routing if the clock is generated inside ...
    (comp.arch.fpga)
  • Re: H8S 2674R All Module Clock Stop Mode??
    ... >pins were inputs). ... >standby, setting and not setting the OPE bit in the sbycr register. ... >software standby as they are in all module clock stop. ... >current consumption. ...
    (comp.arch.embedded)
  • Re: Division and right shift in python
    ... I would like to do a floor division by a power of 2 in python to make it ... t1 = clock() ... 10000000 loops, best of 3: 0.113 usec per loop ...
    (comp.lang.python)