Re: eliminating CMRR problems -- was, 3 dB bandwidth

Mike Monett wrote...
>
> This is an update on cascode transistors in SPICE:
>
> mike wrote:
>
> [...]
>
>> I tried stacking NPN's and PNP's in a complimentary emitter follower
>> with a crossover reducing resistor between the bases and emitters.
>> It looks like this may work. It could be extended to any desired
>> voltage with very low power consumption and reasonable bandwidth.
>>
>> One problem was trying to model it. The version of SPICE I use does
>> not like having the op amp supply voltages track the input signal,
>> and it gave very wierd output signals. I tried several op amps with
>> similar results and finally found the UA741 barely works in this
>> circuit.
>
> It turns out the problem was having the collector of one transistor feed
> the emitter of the next in the stack. Apparently SPICE doesn't like
> handling leakage currents in series. Adding a 1,000 megohm resistor
> across each transistor solved the problem, and the simulation now runs
> much better.
>
> One thing I'll have to watch out for. Shorting the output to ground seems
> to saturate all the transistors in the stack except one. This now has the
> full supply voltage across it. It will blow, of course and probably
> short. This would place the full supply voltage across the remaining
> transistors, which would also likely blow. Like John says, it is probably
> a good idea to add some series resistance to limit the resulting
> shrapnel.
>
> With a low value of load resistance in place of a short, the stack seems
> to saturate in a peculiar manner. With three transistors in series, the
> one closest to the op amp saturates first, then the middle one. This
> leaves the ones connected to the supply voltage to handle the full load
> current. I'll have to ponder a while to figure out why they saturate in
> such a predictable sequence, but it seems to be real and not a SPICE
> artifact.

According to spice, if the output is instantaneously shorted in my
design the series MOSFET transistors nicely ** share the voltages,
which is a natural outcome of their matched Coss capacitances in
series. Each FET's operation is dominated by its Ciss, which holds
its gate voltage steady just after the event. Each one continues
to conduct at the same current, and they then progress together to
another current and to the current limit.

** Except for one MOSFET, the bottom control FET. For the case of
a full negative output just before the short, this part can reach a
high voltage and avalanche. However, the avalanche current is well-
controlled by the other FETs and is completely innocuous, since the
design provides for the current-limit times full avalanche voltage
to be an acceptable short-term power level. So it doesn't blow.


--
Thanks,
- Win
.

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