Re: eliminating CMRR problems -- was, 3 dB bandwidth

Mike Monett wrote...
>
> Mike Monett wrote:
>>
>> Update on cascode MOSFET's:
>>
>> I tried strings of 2, 3, and 4 NMOS and PMOS in series. [snip]
>
> OK, I think I found the solution. Just drive the gates of the mosfets with
> complimentary bipolar. The bias string can be very low power and still give
> enough base current for the transistors to drive the input capacity of the
> mosfets.
>
> I tried two NMOS and PMOS in series with one NPN/PNP driver for each pair.
> The improvement was dramatic. No turn-on transient was visible on the gates.
> It followed a 5KHz 1,900V p-p sine wave with a 50k || 50pF load with no
> problem.

One finds much higher-voltage N-type FETs than P-types, so I've been using
all NMOS strings, in a totem-pole push-pull circuit. With a Darlington BJT
to drive it at the bottom, for higher transconductance and predictable Vbe.

I gather your setup is the common NMOS + PMOS follower circuit? If so,
what PMOS parts are you using and what is their voltage rating? Also,
how are you getting the 5KHz 1,900V p-p sine wave to drive the two NMOS
and PMOS push-pull output with?

Are your measurements real, or *Ahem* Are they just spice measurements?
If so, did you bench-vet your MOSFET's subthreshold model? The standard
models are completely masssively defective, but in a way that makes the
FET's transconductance appear to be very high at low currents, say under
100mA, which improperly wipes out much of their high Ciss problem, which
can then make linear circuits appear to work much better than in real life.


--
Thanks,
- Win
.