Re: eliminating CMRR problems -- was, 3 dB bandwidth

Winfield Hill wrote:

[...]

> One finds much higher-voltage N-type FETs than P-types, so I've
> been using all NMOS strings, in a totem-pole push-pull circuit.
> With a Darlington BJT to drive it at the bottom, for higher
> transconductance and predictable Vbe.

> I gather your setup is the common NMOS + PMOS follower circuit? If
> so, what PMOS parts are you using and what is their voltage
> rating? Also, how are you getting the 5KHz 1,900V p-p sine wave to
> drive the two NMOS and PMOS push-pull output with?

> Are your measurements real, or *Ahem* Are they just spice
> measurements?

> If so, did you bench-vet your MOSFET's subthreshold model? The
> standard models are completely masssively defective, but in a way
> that makes the FET's transconductance appear to be very high at
> low currents, say under 100mA, which improperly wipes out much of
> their high Ciss problem, which can then make linear circuits
> appear to work much better than in real life.

> Thanks, - Win

Win,

Everything is in SPICE to evaluate different configurations. Parts
selection comes later when I am pretty sure it will work. The basic
configuration is the floating op amp driving an inverting stage as
you suggested earlier.

So far the complimentary NPN/PNP bipolar follower has the best AC
performance, but it is difficult to protect against overload. A
plain NMOS/PMOS follower with multiple mosfets has extremely poor
bandwidth and large turnon transients due to the high gate
resistance. The resistance is across the supply voltage of 1KV, so a
low value would waste power.

Driving the mosfet gates with complimentary bipolar followers seems
to eliminate this problem. Adding small (30pF) caps across the bias
resistors seems to allow much higher bias resistance and still keep
good ac response.

I searched google groups and downloaded most of the threads on high
voltage amplifiers, so I am familiar with your discussions about
mosfet subthreshold characteristics.

In this case, the device is being used as a follower, so I believe a
better model would only change the gate voltage a small amount. The
low impedance of the complimentary driver seems to eliminate the
problems with high input capacity. Is this a reasonable assumption
to go on?

The sine and pulse signals are of course generated in SPICE. In the
target application, it would be desirable to minimize the transient
loading when a probe is touched to a circuit. SPICE makes it easy to
evaluate different methods, and a simple rc filter with 1 meg with 5
pf to ground at the input to the op amp looks like it might work. Of
course the resistor has to be able to handle the voltage, so five
200V resistors in series might work.

I am looking for very low leakage diodes to protect the input of the
op amp. There are some posts in the archives on this topic, and I
believe some mention different LEDs may be suitable. Fortunately the
voltage across the diodes should be close to zero.

The overall bandwidth is limited by the op amp. Since I am
interested in low offset and very low input bias current, I expect
the bandwidth to be less than 10 KHz.

I don't expect to be probing 2KV p-p signals at 10KHz anytime, but
it would be nice to be able to measure 60Hz without having to change
probes. So there is little need to try push the circuit to extreme
bandwidths, and the input filter will probably be a convenient place
to limit the bandwidth to something reasonable.

The problem of oscillation with high voltage mosfets in the linear
region remains. There were a few suggestions in the archives on
adding resistors in series with the gate to kill the oscillation,
which is pretty much a standard technique.

I did find some references to high voltage amplifiers in AOE, so I
am in the process of trying to locate a copy.

Mike Monett
.