Re: basic ECL question

John Larkin wrote:

> On Wed, 13 Jul 2005 01:03:50 GMT, Joerg
> <notthisjoergsch@xxxxxxxxxxxxxxxxxxxxx> wrote:
>
> >Hello Mike,
> >
> >>>>The cure was to lift pin 16 (gnd) and install a small ferrite bead. The problem
> >>>>disappeared on the next run and we never saw it again.
> >>>>
> >>>>What caused it, and what can we do to prevent things like that in the
> >>>>future?
> >>>
> >>>I have no idea... 'twasn't my design. As others have discussed here,
> >>>followers can go oscillatory with capacitive loads. Maybe it was
> >>>something like that.
> >>>
> >> Not yours? Oh well, too bad. It seems all the good problems were with
> >> parts you had nothing to do with:)
> >
> >So who dunnit? ECL wants to see a nice termination or a line with a
> >matching termination. Anything deviating from that can look like an L, C
> >or worse to the ECL chip. On a wire wrap board we even had an FM radio
> >go completely silent when the designer fired it up. Oops. The trace on a
> >fast scope coupled in with a loop looked like a wild rodeo. It was
> >singing from all kinds of places. Then we did it again as a soldered
> >board with the wires neatly fastened to the plane and twisted. Now it
> >was clean like a whistle. Same with the layout.
> >
> >I have also seen on oscillating ECL driver on a neatly laid out board.
> >They hadn't stuck to the stripline formulas too religiously, or probably
> >not at all. So we did the layout again, same pattern but correct trace
> >widths and no more 90 degree bends. Then it worked fine. I guess that
> >must be the reason why the ECL data books contain the impedance calcs
> >for traces.
> >
> >Regards, Joerg
> >
> >http://www.analogconsultants.com
>
> I've found ECL (and the faster EclipsLite) to be very well-behaved on
> multilayer boards. In fact it's very quiet, without the nasty glitches
> you get from fast CMOS logic. We just did some GigaLogic designs, the
> stuff with 40 ps edges, and it was super-clean (it should be, for $35
> a gate!)
>
> ECL also has a very low delay tempco; the EclipsLite stuff runs below
> 1 ps/K typically, far better than any CMOS part. Too bad it's an
> expensive power hog.
>
> 90 degree bends and vias are no problem with 10KH or even EL edges.
>
> John

90 degree bends look real *** though and provide stress to the trace that may make the
board less tolerant of mechanical forces. Ahhh for the days of manual tape-ups ! Curvy
tracks...... I loved doing them. You get better board density that way too.

Graham


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