Re: rise and fall time




"Joerg" <notthisjoergsch@xxxxxxxxxxxxxxxxxxxxx> wrote in message
news:EdyEe.6238$_%4.1894@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx
> Hello M. Smile,
>
>> No clock would be applied.
>> It is a cheap way I'm experimenting to send clock pulses or reset pulse
>> on the same line: clock input directly connected to this line and reset
>> input through a 1mS RC filter. Sending short pulses (14uS on/46uS off in
>> my case) would not be enough to rise significative voltage on reset input
>> after the RC filter but clock input would work as intended. On the other
>> hand, sending a long pulse (say 5mS to be sure) would rise voltage enough
>> at reset input to reset the counter.
>
> For greater peace of mind I would look into adding a CD40106 Schmitt
> inverter before each input. For the reset that would be after the RC
> filter. It is cheap. Just keep in mind that now the assertion levels will
> be inverted.
>
> I have done a lot of slope dependent and duration dependent switching with
> CD40106 chips. They are great.

I may consider this if it proves to be unreliable.
I'm just trying to do as much as possible with less chips, otherwise I go
with microcontrollers.

Thanks!
M.S.


> Regards, Joerg
>
> http://www.analogconsultants.com


.



Relevant Pages

  • Re: Mixed clocked/combinatorial coding styles
    ... I wouldn't use a device input that performs a device wide reset ... as a clock input had better be able to cope with the clock shutting ... The outputs of the shift registers become the reset signals ... requirement to go active at the end of configuration, ...
    (comp.lang.vhdl)
  • Stupid Newby Question: VHDL/CPLD Shift Register Reset Problem
    ... Let's say I'm building a simple 8-bit shift register (serial in, ... IO_GCK2 clock input of the CPLD. ... The reason I'm asking is because I am having some reset problems when ... end SerialToParallel; ...
    (comp.lang.vhdl)
  • Re: how to build a clock with pulse for the hours!
    ... hammer that strikes a metal gong. ... It's a novelty clock! ... RESET "R" input goes false. ... then, when the next pulse comes out of the divide-by-216000 counter, an ...
    (sci.electronics.basics)
  • Re: DCM problem with a SPARTAN-3 from xilinx: large range of clock input signal
    ... to the reset pin, but when I do that is just stays in reset. ... Maybe it's better to explain how I now reset the DCM. ... I've got two counters, one counts the incoming clock signal and the ...
    (comp.lang.vhdl)
  • Re: alternate synchronous process template
    ... two separate processes (one with async reset, one without), in one ... to generate the reset signal to everything else in the design and then ... first rising edge of the clock the outputs are in a different state. ...
    (comp.lang.vhdl)