Re: The variable bit cpu

"Skybuck Flying" <nospam@xxxxxxxxxxx> wrote in message
news:dcgrv9$eu3$1@xxxxxxxxxxxxxxxxxxxxxxxxxx
> It works simply like this:
>
> Each "data bit" has a "meta data bit".
>
> The meta data bit describes if the bit is the ending bit of a possibly
> large
> structure/field.
>
> The meta bits together form a sort of bit mask or bit pattern.
>
> For example the idea is best seen when putting the data bits
> and meta bits below each other.
>
> data bits: 01110101110101101010101
> meta bits: 00000000100010001100001
>
[...]
>
> The above example then looks like this:
>
> data bits: 011101011#1010#1101#0#10101
> meta bits: 000000001#0001#0001#1#00001
>
> (The # sign is too indicate to you where the variable bit fields are.)

Are you familiar with the instruction sets of any general-purpose
microprocessors (x86, ARM, etc.)? If so, what changes to the instruction set
would you make to address data in this format? Remember that memory buses do
have to have a fixed (or at least maximum) width--a 16-bit parallel flash
chip has 16 physical data pins, i.e. little pieces of metal that solder to
the printed circuit board, one for each bit in the word. That is not
something you can change at run time! Similarly, registers in a CPU must
have a fixed length, or at least some maximum width; each bit in a register
corresponds to a physical flip-flop and some other circuitry on the chip.

How do you think this would work with arithmetic operations, for example?
The hardware to perform operations like addition and subtraction operates on
many bits in parallel, for speed. That means that the chip designer must
decide how large of a number the CPU can add in a single instruction (or in
a single cycle at least). If he designs a 32 bit-wide adder, then the CPU
will be able to add two 32-bit numbers very fast, probably in a single
instruction cycle. If he chooses an 8 bit-wide adder, then the CPU would
take much longer to do that, at least four cycles. However, the 8-bit adder
consumes much less area on-chip than the 32-bit adder. How would you handle
that with your 'variable bit' idea?

Your format allows arbitrary-length fields, but it requires 2*n bits to
store n bits of data. A fixed and predefined layout would only require n
bits to store n bits of data. Can you think of a good compromise between
those two extremes? Do you expect many small fields, or fewer large ones?
What is the distribution? I think that you will find that almost any scheme
is nearly optimal under some set of assumptions, but what kind of
assumptions are reasonable? Regardless of the format that you choose, do you
think that it is necessary to make changes to the instruction set to support
that format? If so, what does it gain you?

The design of a new instruction set is a very specialized area. Most of the
people who design new instruction sets have a very good idea of what kind of
problems people use computers to solve, and what kind of instructions make
life easy for the compiler (and what language someone will want to write a
compiler for), and so on.

If you are interested in this field then maybe you would find it more
rewarding to look at little problems. For example, your pocket calculator
probably has some sort of custom microprocessor in it. What kind of
instructions would you need if you only want to build a four-function pocket
calaculator, and nothing else? That is a much more manageable sort of thing
to design, because the problem that you are trying to solve is much more
constrained.

Jonathan


.

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