Re: Data throughput of embedded ethernet


"Aubrey McIntosh, Ph.D." <newsposter@xxxxxxxxxxxxxxxxxxxxxx> wrote in
message news:11fsepefir40c4a@xxxxxxxxxxxxxxxxxxxxx
>
>
> Richard H. wrote:
> >
> > Then, finding a creative way to load the data directly from the ADC into
> > the Ethernet NIC will be key to how many cycles will be needed on the
> > MCU. (E.g., setting the NIC in bulk write mode, toggling the ADC data
> > onto the bus, and toggling the NIC to latch the bits; a la DMA
> > controller style.)
> >
> > If the MCU doesn't need to manipulate the data (e.g., even for
> > checksums), you can avoid the overhead of copying it into the MCU and
> > then right back out; this is the most frequent and biggest operation, so
> > it's a big factor. Part of this will be driven by whether the ADC is
> > being read serially or 8/16/24 bits wide, and the size of its buffer (if
> > any). (I.e., if it can sustain pauses in the stream, and whether the
> > MCU needs to handle all the data.)
> >
> > There are 3 ISA-style 100Mb chips out there; the rest are integrated or
> > PCI.
> > http://www.asix.com.tw/emb-non_ax88796.htm
> > http://www.davicom.com.tw/eng/products/dm9000.htm
> > http://www.smsc.com/main/catalog/lan91c111.html
> > (http://www.edtp.com/ recommended for ASIX protos)
> >
> > Cheers,
> > Richard
>
>
> Has anyone made a card where the "ADC finished" signal feeds a counter
> and a DMA circuit on memory that is shared with the CPU?
>
> Some Xilinx part could compute the CRC values in parallel so that no CPU
> overhead would be used for that. I suppose the same part would pre-fill
> the address, protocol, and other packet headers as well as putting the
> first user data address into the counter.
>

Actel has an ethernet core module.. add some extra logic to control the ADC,
put the results directly into the ethernet controller's memory and send..
minimal cpu overhead..




.

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