Re: this is getting crazy
- From: John Larkin <jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Sat, 20 Aug 2005 09:39:48 -0700
On Sat, 20 Aug 2005 11:31:20 -0400, Greg Neff <greg@xxxxxxxxxx> wrote:
>On Fri, 12 Aug 2005 11:35:09 -0700, John Larkin
><jjlarkin@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
>
>>BOARD STATISTICS REPORT -- 22D470A_5_1.pcb -- Fri Aug 12 10:44:09 2005
><snip sobering statistics>
>>
>>
>>John
>
>I feel your pain. Did you use an autorouter on this?
No! We told our layout guy what things needed to be connected to which
FPGAs, told him which pins were unassigned i/os, which ram pins he
could scramble, and let him optimize the routing. So most of the
serious stuff is clean, via-free, spiffy-flowing layer 1 traces. Then
we back-annotate the schematic and run a perl script that crunches the
PADS netlist and gens Xilinx pin constraint files.
>We have given
>up on autorouters. Even Specctra can't manage to do a decent job on
>our dense boards, and managing signal integrity after autorouting is a
>nightmare. So now we manually route boards, even with 1,000+
>components. Believe it or not, it takes us less time and it costs us
>less in the long run.
>
Oh, I do believe it.
>We have found that the key to a (relatively) painless layout is lots
>of planning prior to routing.
Placement, placement, placement.
>
>I always select pinouts on CPLDs, FPGAs, resistor networks and
>connectors (where possible) to make the layout as easy as possible.
>It takes time to do this, but this time is saved during layout. This
>approach provides shorter signals with fewer crossovers, which is
>always a good thing.
>
As I said, we let our layout guy do it. He does an excellent job, even
though he doesn't understand the functionality at all. We review it
along the way to make sure it will be electrically nice.
>I try to select component packages that will provide for the best
>physical flow of signals on the board. In this respect a larger
>component package may provide better real estate utilization and/or
>signal flow than a smaller package. Thinking about all of this stuff
>during the schematic phase pays off huge dividends later.
Right.
>
>The three most important things about real estate are location,
>location and location. This applies to circuit boards too. I group
>parts in OrCAD to make the initial placement easier. For critical
>groups we may even route and lock it prior to placing other
>components. We spend lots of time on the group and component
>placement. A well placed component is an easy to route component.
>
>I group nets in OrCAD so that these can be easily seen during routing.
>Also, I prepare a list of critical nets (clocks, strobes, resets, diff
>pairs, etc.) so that these can be properly managed.
>
>With this approach we save time on design, save layer count, and
>reduce the risk of having another board spin because of signal
>integrity problems.
The thing that doesn't work is the "throw it over the wall" method you
see in big companies or with outside contractors. While a serious
board is being laid out, we work with our layout guy constantly, and
we discuss things, and we often change the design to help him make a
beautiful layout. 16-bit bus too nasty? OK, we can live with 8.
John
.
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