strained Si cmos
- From: "jason" <cheanglong@xxxxxxxxx>
- Date: 27 Aug 2005 23:40:46 -0700
Hello All
Anyone knows the process flow of a strained Si cmos device?
The drain and source region is strained as well?
Kindly recommend any links or papers touch on the details of
fabrication
Thank you all
Jason
.
- Follow-Ups:
- Re: strained Si cmos
- From: Sylvain Munaut
- Re: strained Si cmos
- Prev by Date: Normal 4-pin USB to USB-OTG?
- Next by Date: Re: do high current, high inductance inductors even exist (say 5A, 5mH)
- Previous by thread: Normal 4-pin USB to USB-OTG?
- Next by thread: Re: strained Si cmos
- Index(es):
Relevant Pages
|