Re: Strange curves...



Fred Bartoli wrote...
>
>http://www.kemet.com/kemet/web/homepage/kechome.nsf/vapubfilesname/f3102.pdf/$file/f3102.PDF
>>> curves at bottom of page #57.
>>>
>>> Some strange things.
>>> Bizarre...
>
> Look more carefully: impedance behaviour versus chip size.
>
> Fig 4. 100p 0805 vs 0603: 0805 size resonates higher than the 0603 size.
> Fig 5. ESL lowers with increasing size.
> Fig 6. ESL doesn't depend on chip size, but depends on dielectrics.
> Fig 7. ESL doesn't depend on size.
>
> Looks like strange physics at work, or someone screwed things up.

Measurements at different times, with different zero-inductance cals.
I have the two HP instruments used to take these measurements, with
the rather spectacular-looking test fixtures for these caps. There
are several ways to set the zero-inductance value for the fixture,
each of which has validity its own condition. For example, if you
zero with a metal slug the size of the cap in place, you'll measure
the additional inductance of the part, generally close to zero. If
you zero with no slug, and then measure a part, you'll primarily see
the inductance from a conductor the size of the part. HP's manuals
don't specify how one should take the measurements in this regard,
but to the extent they do, and tidbit accessories are provided, they
favor the first technique, which shows no effect from physical size.

Both are valid measurement methods, but the data isn't very useful
unless you know the measurement condition. This issue obtains in
actual use as well, where one is probably best off ignoring catalog
curves, his own measurements, etc., and calculating or using rules
of thumb for specific PCB layouts. In the end the only measurement
that counts is the in-place resonant frequency.

I wouldn't be surprised if Kemet's catalog curves for ESL came not
from actual measurements, but from rules of thumb, different rules
at different times for different parts, put together on one plot at
the end by a draftsman type. Kemet's plots show ESL ranging from
0.7 to 2nH, which is about right for various optimized PCB layouts
and resonant conditions.

In actual practice, the nasty parallel resonance at a bypass-cap
node due to the PCB wiring inductance to the larger "sea of caps"
is what one must worry about, and damp out with some parallel esr,
and here the cap's series ESL value scarcely matters. The series-
resonant impedance dip at a higher frequency isn't of much concern
either.


--
Thanks,
- Win
.



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