Re: Need help regarding flash memory options

No. Access to the flash device is not really all that software
intensive - at least not much more so than talking to a serial one over
SPI. Parallel access off general purpose ports is going to require
something like three or four port accesses per read or write. Access
to SPI is going to require one to set it up, but then you have to wait
for it to finish.

That's just communicating with the chip. To accomplish anything
meaningful like reading data, or writing it, or erasing blocks, or
mapping around errors, is going to require about the same amount of
work either way. Regardless if the interface is SPI or parallel, you
are going to have to issue commands to the chip to do each of these
things - command, address, data, in some cases a whole block of data
without more command or address.

Parallel access is no harder to code than getting the SPI ports on an
unfamiliar micro up and running. It's likely faster at run time, or at
least not appreciably slower. And the complexities of software to do
anything usefull with the flash are the same, because the command sets
and underlying NAND cell behaviour are pretty similar regardless of the
physical interface used.

If you really want to avoid all of this, buy an embedded O/S with flash
routines.

.

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