Re: help for VHDL and DAC

Hi, thanks Pete:
I will gerenate a stream of data from the FPGA, so it will be
parallel output. The clock rate will be 50kHz, that means it is
50kSamples/sec. But how can I set the data into the Series Register?
How do I do in ISE7.1? What do you mean with UART?
About the filter, the problem is the following: I have a step
function from the output of the DA converter, each step has a duration
of (1/50k)s. But I want to smooth this signal, so I should implement a
low pass filter, I would think the cut off frequency would be 50kHz, or
no? I don't think this has anything to do with the Nyquist limit.
Thanks
Brandon Xin

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