Re: LVDS driver in SERDES


Iterativeend wrote:
> TI - SN65LV1021 / SN65LV1212
> NS- DS92LV16

Ah, you are talking about the low-speed (100-400 Mbps) 1:10 LVDS bus
extenders. They do use a start/stop bit setup to keep word alignment
across the link, but the device does all that for you - so I'm not sure
what your original question was about.

> I guess the 1st few cycles will be lost and till the lock is held,
> there should be no problem.

More than a few... if you'll notice in the SN65LV1021 data ***, there
is a whole page dedicated to the topic of synchronization between the
transmitter and receiver. The "rapid synchronization" mode takes
6+1026 TCLK cycles. The "random-lock" mode presumably takes even
longer.

> I am more confused abt embedding the clock now.

>>From page 3 of the data***: "When the deserializer detects edge
transitions at the LVDS input, it attempts to lock to the embedded
clock information. The deserializer LOCK output remains high while its
PLL locks to the incoming data or SYNC patterns present on the serial
input."

In reading the data***, there almost seems to be an implication that
the REFCLK for the receiver must be the exact same frequency as TCLK -
so the "clock recovery" may just be used for phase aligning the PLL'ed
REFCLK with the incoming data.

Marc

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