Re: Input stage mess

On Mon, 28 Nov 2005 22:34:40 +0100, "Fred Bartoli"
<fred._canxxxel_this_bartoli@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:

>Well, I've finally got doing that low noise preamp: the target is
>200pV/rtHz, bandwidth from 0.1Hz (with provision for 1/f noise) to 1MHz.
>
>Lots of interesting pbs to solve. One remaining thing is some stability
>issue wrt to cable/generator impedance.
>The input stage will be 4 to 6 paralleled Interfet's IF3602. They'll work at
>a low servoed 1V VDS to minimze thermal noise problems.
>Under those bias condition the JFet will show about 300pF Cgs and 180pF Cgd.
>The Jfet is servo-cascoded so that amounts to and equivalent 480pF Cgs.
>The closed loop preamplifier show an input impedance that has a painfull
>negative real part input admittance.
>Admitting a first order response, the input admittance is:
>
> Cgs w^2
>Yin = -------------- with WT = 2 pi GBW and beta= feedback network
>attenuation
> WT beta + j w
>
>This translate to an equivalent parallel network:
>
> 2 2 WT beta
>Rin(w) = - ------------ - ------------
> Cgs WT beta Cgs w^2
>
> 1 Cgs w^2
>Cin(w) = --- . -------------------
> 2 w^2 + WT^2 beta^2
>
>Now the figures:
>designing for a 10 loop gain (WT beta) at 1MHz this give a low -12R for the
>real part at high frequencies and will give a nice oscillation with the
>input cable impedance (estimated between 300nH & 500nH).
>As the generator impedance is low, the easy way to deal with this could be a
>serie RC in parallel with the input (sort of 2-5 nF and under 12R resistor).
>Unfortunatly a 10R resistor is 410pV/rtHz and 41pA/rtHz which translates to
>about 130pV/rtHz across the 0.5uH cable inductance at 1MHz. A bit more than
>I would like.
>More, this 10R is dangerously close to the -12R value, which didn't
>accounted for additionnal parasitic poles and will probably be lower.
>Plus cable resonance with the input capacitance will rise the noise level.
>
>I can't insert a damping resistor in series with the gate connexion for
>noise reasons (200pV/rtHz is a super low 2.5R noise resistance).
>
>I've thought of a lot of schemes for neutralizing Cgs, but found nothing
>practical.
>
>I also can't run the input stage open loop, which would solve this issue but
>will raise some others.
>
>Any idea?


Can you post a schematic, real or simplified?

John

.

Relevant Pages

  • Input stage mess
    ... Under those bias condition the JFet will show about 300pF Cgs and 180pF Cgd. ... The closed loop preamplifier show an input impedance that has a painfull ... the input admittance is: ... Plus cable resonance with the input capacitance will rise the noise level. ...
    (sci.electronics.design)
  • Re: Input stage mess
    ... I've finally got doing that low noise preamp: ... >>a low servoed 1V VDS to minimze thermal noise problems. ... >>negative real part input admittance. ... >>I can't insert a damping resistor in series with the gate connexion for ...
    (sci.electronics.design)
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