Re: Input stage mess

Fred Bartoli wrote:


For the problem of interest here, it comes from the differential input
voltage which rises 6dB/oct with a 90° shift wrt to the input voltage (due
to the open loop gain pole) and the JFETs capacitances across the inputs
(1.45nF between the preamp in+ and in-) which introduces another 90° shift
for the current injected at J1 gate, hence the negative resistance.
Exactly the same pb as an emitter follower loaded with a cap.



Hmm. Looks like the origin of the problem is the overall feedback. Do you really need the virtual ground? If not, how about making the input stage a feedforward 20-dB stage instead, and adding the feedback amp afterwards?

Since your JFETs will be reasonably linear at that I_D, the feedforward path will have low gain, and hence you can use a higher-noise amp to generate it. This of course will require a bit of tweaking.

BTW are the 10-uf capacitor leakage and gate current really low enough to use a gigaohm gate leak resistor-- 1pA ==> 1 mV? And do you really want a 3 hour time constant on your bias circuit? Oh, and you have two nearly perfect integrators in your dc feedback loop, which will cause nasty behaviour.


Cheers,

Phil Hobbs
.