Re: Input stage mess

Thanks Phil.
Comments inserted below.


"Phil Hobbs" <pcdhSpamMeSenseless@xxxxxxxxxxxxxxxxxx> a écrit dans le
message de news:438C7D09.4090408@xxxxxxxxxxxxxxxxxxxxx
> Fred Bartoli wrote:
>
> >
> > For the problem of interest here, it comes from the differential input
> > voltage which rises 6dB/oct with a 90° shift wrt to the input voltage
(due
> > to the open loop gain pole) and the JFETs capacitances across the inputs
> > (1.45nF between the preamp in+ and in-) which introduces another 90°
shift
> > for the current injected at J1 gate, hence the negative resistance.
> > Exactly the same pb as an emitter follower loaded with a cap.
> >
> >
>
> Hmm. Looks like the origin of the problem is the overall feedback.

Yes.

> Do you really need the virtual ground?

Which virtual ground are you speaking about? The whole preamplifier is
non-inverting.


> If not, how about making the input
> stage a feedforward 20-dB stage instead, and adding the feedback amp
> afterwards?
>
> Since your JFETs will be reasonably linear at that I_D, the feedforward
> path will have low gain, and hence you can use a higher-noise amp to
> generate it. This of course will require a bit of tweaking.
>

Hmmm, feedforward is one thing I forgot to think about. I can smell some
interesting idea here but right now I fail to see exactly what you have in
mind. Can you sketch something?

One thing I can't do is getting the Jfets out of the feedback loop. The
preamplifier will have 2 purposes:
1) investigate noise in a _very_ low noise power supply (200nV rms)
2) measure the supply transient recovery to an injected charge. The measured
recovery is about 200nV, so expected aberrations (electric and thermal)
should be lower than 50nV,... excluding noise :-)
Unfortunatly the initial transient can be a few 100mV, up to about half a
volt, and will induce nasty thermal tails if the jfets were working open
loop.
Working with an hypothesis of 1mV/K offset gives 50uK for the stability, and
200pV/rtHz translates to 0.2uK/rtHz, so some serious power stabilisation is
in order there.


> BTW are the 10-uf capacitor leakage and gate current really low enough
> to use a gigaohm gate leak resistor-- 1pA ==> 1 mV?

I've measured some of the Jfets at under 2pA gate leakage under these
conditions, much better than the given specs and this is for a few boxes, so
that's OK for me. I was pleasently surprised because these are pretty big
transistors and this will simplify my already enough complicated life.

The 10uF are specified at 25000s minimum time constant, i.e. 2.5 gigaohm.
The input DC component is about 10V and I've again measured some samples
much better. Again I can select so it's OK too.

And do you really
> want a 3 hour time constant on your bias circuit?

An unfortunate side effect of the low frequency requirements.
I've not shown some speed up circuitry which was not relevant to the pb.

The 10uF is mandatory because of the gate shot noise rising the input noise
at low frequency, and the bias resistor has to be 1Gohm because I obviously
don't want its current noise be greater than the gate noise current.

> Oh, and you have two
> nearly perfect integrators in your dc feedback loop, which will cause
> nasty behaviour.
>

Oops, yes I obviously missed a zero somewhere :-)


--
Thanks,
Fred.


.

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