Re: Input stage mess
- From: fpm@xxxxxxxxxxxxxxxx (Frank Miles)
- Date: Tue, 29 Nov 2005 18:18:44 +0000 (UTC)
In article <438c1d1b$0$21209$626a54ce@xxxxxxxxxxxx>,
Fred Bartoli <fred._canxxxel_this_bartoli@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
[snip]
>> >Well, I've finally got doing that low noise preamp: the target is
>> >200pV/rtHz, bandwidth from 0.1Hz (with provision for 1/f noise) to 1MHz.
[snip]
> 85mA 85mA
> to to
> 125mA 125mA
>
> V V
> | |
> +------------------------+--------.
> | | | |
> .--+ .--+-----+--------. | |
> | .-.R3 | .-.R4 | /| | | |\ |
> ---| | ---| | >| /-|-' '-|-\ |<
> ---| | ---| | |-< | | >-|
> | '-' | '-' /| \+|--+--|+/ |\
> '--+ '--+ | \| | |/ |
> | | | 2 V |
> clamp --. | .-------------------' |
> | | | | | | ___
> | | | | | .---------------------|___|-.
> 10u | J1 |-+ | +-|J2 | | | R2 |
> || | | | | | | ___ | |\ |
>in -+--||--+--->|-+ | +-|<-------+-|___|-. | .----|+\ |
> | || | | | | |5mA R1 | 5mA| | | >-+-out
> .-. .-. '---+---' | | GND | | GND .-|-/ |
> | | | | | | V V | | |/ |
> | | | | | .-----------------------. | |
> 1M'-' '-'1G | | Precision |--+--||--+
> | | V | current mirror | .-.
> GND | 160mA '-----------------------' | |
> | to /| | |
> | 240mA /+|-GND'-'
> '------------------------------------------+-< | |
> | \-|-+---'
> | \| |
> '-||---'
>
>
>
>J1 and J2 are 4 to 6 paralleled IF3602, no source degeneration (noise),
>running at 20mA/transistor.
>R3 and R4 are one per transistor and 50R (1V across the Jfet, 1V across the
>R)
>
>The feedback path has _low_ impedance (1 fb path per jfet, 1R/27R).
>
>As you can see, nothing terribly fancy. All lies in the details (like the
>subject of this post).
>
>For the problem of interest here, it comes from the differential input
>voltage which rises 6dB/oct with a 90° shift wrt to the input voltage (due
>to the open loop gain pole) and the JFETs capacitances across the inputs
>(1.45nF between the preamp in+ and in-) which introduces another 90° shift
>for the current injected at J1 gate, hence the negative resistance.
>Exactly the same pb as an emitter follower loaded with a cap.
Challenging!
I don't know if you can meet the noise specs by going down this pathway,
but if the series RC shunting the input adds too much noise, I think you're
going to have to bootstrap your input circuit to get rid of the negative RC
Zin. This will have to operate at high speed -- not at the slow speed of
the feedback loop. Of course there are limits to this approach as well, but
with the right topology you may be able to use a pure capacitance between J1's
gate and an appropriate virtual ground input node to provide a high frequency
boost to J1's source. This has been done, for example, in a few oscilloscope
vertical inputs to provide a wider-band input while reducing the dribble-up
behavior of real follower circuits which have capacitive loading.
Did you say anywhere what the spec had to be for input capacitance? Perhaps
a bit more HF energy can be stolen from the input? Some other games might
be played if that is allowed. From your resistor values it looks as though
Rin must be high.
Unfortuantely I don't see any way to use the capacitive feed-beside method with
your existing topology. It really needs a follower initial input stage.
This fixes your Zin problem but reaching your noise target will be fun.
I confess I haven't gone through the numbers to determine whether that is
possible with such a different structure. Good luck!
-frank
--
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