Re: HCT4051 leakage

"John Larkin" ...

> The small errors we're seeing may be due to cmos switch leakage, but
> the error TCs are looking linear enough that leakage is probably not a
> big issue... it should be sorta exponential on temperature, and we're
> not seeing that.
>
> Switch resistance doesn't matter here as long as it's constant for the
> duration of the two measurements. We're taking about 130 millisec for
> each measurement, 260 total. It might be that the current (about 6 mA
> when we're measuring a 100 ohm RTD) is heating the cmos switch enough
> to give it a r-versus-t curve that matters. 6 mA, 75 ohms typ, gives
> around 3 milliwatts in the switch. The HCT switch is about 75 ohms and
> increases about 0.25 ohms/K. So, what's the thermal coefficient of one
> fet in an HCT4051? 1000 k/w maybe?
>
> If it increases 3K as a result of the switched current, we'll have
> 0.75 ohms increase, serious by our standards. But what's the thermal
> tau?


Have you considered the thermal gradient in the chip may cause offset
voltages from the thermocouple like junctions (also Al-Si bonding points
etc) in the chip? I've seen 10..100 uV offsets when a 4051 chip (turned ON)
was next to a dissipating element. What's the equivalent offset voltage you
see?

Arie de Muynck


.

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