Re: PLL and SYNC question

to Tim Wescott

Thank you for the quick answer.

> What do you mean by error-linearity?!?

I didn't mean the phase comparator output but transient phase
error signal after the loop filter (that must be fed to the VCOin).
I implemented 1st order passive low pass filter as the loop filter.
You know in this case you have not the same signal forms if you have
100 Hz or 20kHz loop input.


> Huh? 4046's only work into the low MHz; with big enough capacitors
> they'll work down to the single-digit Hz.

I agree. But I don't use VCO.


> I've implemented software PLLs up to 80kHz on modern DSP chips. You
> need to have a fast DSP to be able to update the control loop at that
> rate, or you need to figure out how to subsample the input without
> messing up. If you can generate a sine wave at 20kHz in your DSP you
> must be turning a routine over at over 40kHz, so I assume you have a
> fast DSP.

Really? Great performance (I'd like to have too).
My DSP is SHARC ADSP21262 running at 200 MHz. I think it's suitable. But
there are another algorithms to be implemented in my design (filters).


> The key is to use a timer for the phase detector. If you have a timer
> capture input you can capture the timer's phase at the instant that the
> input signal happens. If you use the same clock that's generating your
> sine wave for input capture you can easily relate the input phase to
> your output phase.

I used to capture period of the TTL-input by the timer and to generate
corresponding sine wave. This worked very well for 100-Hz but was not
precise for 20KHz input. Did you use 1 timer for the phase detector?
Could you describe the whole process more detailed, please?


> Yes, your loop will be more complex. But with this complexity you can
> buy easy linearization, gain scheduling to account for the changing
> sampling rate as your input rate gets low, and good fast rough
frequency
> estimation to start your NCO at the right frequency and phase for quick
> locking.

Yes, I'd like to implement a software PLL and escape using additional
hardware. Did your implemented SPLL worked for defined frequency only
or for a frequency range, how large was the lock range? My software must
be able to lock to frequencies from 20Hz to 20kHz.

Regards
kirgizz
.

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