calculating parasitic delay for ratioed circuit

I am a student and have trouble figuring out some calculations.

I have a 6 input NOR gate design using pseudo NMOS. So there is only 1
PMOS at the pull up with the gate connected to ground. The size is 15.
The pull down has 6 NMOS in parallel and each has a size of 30.

I have trouble figuring out how to find the parasitic delay. The book
says 52/9. Can somebody please guide me through it?

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