Re: 1Mhz -> 1hz
- From: bill.sloman@xxxxxxxx
- Date: 21 Dec 2005 17:11:27 -0800
theJackal wrote:
> On 21 Dec 2005 02:57:32 -0800, bill.sloman@xxxxxxxx wrote:
>
> >
> >theJackal wrote:
<snip>
> By writing log10^6/ log12 *4 = 22 flip flops
> I was thinking very straight ... Math stretches right where human
> intuition sometimes fails . As I said ask ... and I will explain.
> By dividing by log 12 i was getting to the maximum number of mod 12
> counters which would be 5. With 5 of those you'd have a frequency of
> 1000000Hz /2.48832000E+005 =
> 4.01877572E+000Hz left .
> I'd easily handle that with a Mod 4 counter leaving me with
> 4.01877572E+000Hz/4 = 1.00469393E+000 Hz which is quite good.
> Total number of flip flops = 5*4 + 2 = 22 flip flops ... which is what
> my simple division of logs up there was saying.
But 22 flip-flops isn't quite enough, even if two of them aren't in
divide by 12 packages
I don't think you mathematical exercise took you anywhere useful
> >The real limit is still 20 bistables.
> >
> <grin> If I was you I wouldn't bet my life on that ... I got some
> ideas on beating that limit!
Hmm - ternary logic? I suspose there might be a way of exploiting the
fact that a tri-state output can be in three states ...
> >> Guess. If you can't ask .
I'd love to know what you've got in mind.
> >> You never seem to understand what I say ...
> >
> >Unfortunately, I understand it all too well - as well as what you don't
> >say because you haven't understood the problem well enough to think it
> >through properly.
> I was acting in a subtle manner, read above ... it wasn't easy for
> anyone to guess where the math was pointing to!
Nothing complicated about where it was pointing - the puzzling aspect
was why one would want to point the OP that way.
> >> 2)2^20=1,048,576 You won't get 1Mhz with that . You need some more
> >> hardware there-
> >
> >The question was restricted to D-type flip-flops, and I've already
> >indicated that I'd use one more to produce a tidy reset pulse.
> ummm
> >Obviously, you need combinational logic to make such a counter work.
> >You can use propagation delays through combinational logic to produce a
> >reset pulse which would be very likely to be wide enough to reset all
> >the bistables, but since most logic families don't specify minimum
> >propagation delays, you can't always be absolutely confident of the
> >reliability of such as system. I've used delay lines to solve this sort
> >of problem, but they aren't cheap.
> >
> Regarding the delays I'd measure them before building the circuit. You
> have at least 4 different types and they can amount to 10's of
> nanoseconds which in terms of frequency is a lot . Mostly depend on
> the technology of the logic families being used.
> Then don't forget clock skews.
A pretty good rule of thumb is to assume the minimum propagation delays
to be one third of the maximum delays, but if the manufacturers don't
guarantee it, it is risky to rely on it.
Measuring propagation delays before you build the circuit is sort of
okay, for a one-off. One very fast TTL system I ws involved with at
Nijmegen University relied on exactly that, and the engineer go the
system back about once a year as one of other of the ICs had aged
enough to take its propagation delay outside the acceptable envelope.
So the researchers didn't have an ESR machine for a couple of days
while he shuffled ICs until he'd got it working again. I replaced a
couple of critical components with ECLinPS and we got rid of almost a
nanosecond of pattern-related jitter, as well as the really tricky race
condition.
I essentially completed the design of a properly toleranced system,
using a lot more ECLinPS to deliver much better performance, but the
grant that ran the ESR machine dried up, so it was never built.
------------------
Bill Sloman, Nijmegen
.
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