Re: 1-32 Khz in 1khz divisions

Spehro Pefhany <speffSNIP@xxxxxxxxxxxxxxxxxxxxxxx> wrote:
> On 26 Dec 2005 11:18:11 GMT, the renowned Ian Stirling
> <root@xxxxxxxxxxxxxxxxx> wrote:
>
>>Spehro Pefhany <speffSNIP@xxxxxxxxxxxxxxxxxxxxxxx> wrote:
>>> On Sun, 25 Dec 2005 21:04:32 -0700, the renowned Barry S.
>>> <nntp@xxxxxxxxxxxx> wrote:
>>>
>>>>I need to generate 1khz, 2khz, 3 khz, 4 khz, etc.. up to 32 khz..
>>>>They don't have to be exact.. Each free running, each on their own
>>>>output..
>>>>
>>>>My first inclination was to use counters, but that would be a few
>>>>counters, prescalers, flip flops, etc because the divisions don't come
>>>>out nicely. My second idea was to use a microcontroller with a lot of
>>>>outputs.. E.g. Input A1 gets turned on/off every 1 ms (1 khz)..
>>>>
>>>>Any ideas for an approach?
>>>
>>> If you don't want a bunch of jitter, you're probably stuck with logic
>>> of some kind. A microcontroller is not very appropriate for this,
>>> although I've implemented similar systems with a few outputs (eg.
>>> 0.5/1kHz/2kHz to energize a conductivity probe) with very little
>>
>>If you dedicate the micro, it's not quite so bad.
>>
>>The OP said "don't have to be exact".
>>Let's assume that the frequency can be off by 125Hz, for a total error
>>on adjacent frequencies of 250Hz (5.125 - 5.875 = 250hz).
>>
>>What does this buy us?
>>Well, 16*17*18*19*20*21*22*23*24*25*26*27*28*29*30*31*32 is about 10^18,
>>far too fast to clock the micro of course, at least for a few years.
>>So, the question is, what is the minimum frequency that can be a least common
>>multiple for the inexact frequencies.
>>I don't know how to calculate this, so let's work out about what it might be.
>>
>>32*32.125 = 1026.4
>>
>>At this point I realised it was too early to be thinking, and wrote
>>a 4 line program to give me the answer.
>>Error Freq
>>125Hz 2108Khz
>>75Hz 3356Khz
>>
>>4Mhz also works for 125Hz, 5Mhz for 75Hz.
>>
>>So, let's say we have a micro clocked at a multiple of 4Mhz.
>>How much work is needed?
>>It'skpj l
>
> Decrementing 32 16-bit counters, checking for borrows or zeros,
> toggling output pins and reloading each counter. Unless I'm missing
> something, if it's going to be perfectly jitter-free you can't update
> faster than the worst case of all that stuff, which sounds like maybe
> 300-600 instructions to me, so you'd need a 1.2-2.4GHz micro.

Oops.
Not quite that bad.

I'm assuming that you'll only want some 13 outputs or so - the rest comes
from a couple of chips of external dividers - or another chip.

You only need 4MHz/16KHz = 250, so it's only 8 bits.


Dec counter
Jz set
Nop
Jmp next
set: xor porta, bitmask
sto counter, divisor


So, maybe 4*16, but that still adds up to 288Mhz.

Anyway, if the OP wanted to do the cable-sorting problem using frequencies,
an optimisation would be to use maybe a couple of extra instructions on each,
and run a 5 bit counter from each of these initial counters, and write the
5 bits as one to the output.

So you'd get

16 8 4 2 1
18 9 4.5 2.25 1.125
24 12 6 3 1.5
....

Which'd reduce the problem to something that's doable on a 100Mhz
microcontrollercontroller
.

Relevant Pages

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