Re: PMOS device reversed

On 3 Jan 2006 17:41:05 -0800, "QQ" <q_q_404@xxxxxxxxxxx> wrote:

>>> Latch-up. If your connection was an absolute necessity you could add
>>> an N-well ring around the device tied to +VDD.
>
>I think there may be some freedom with the process. Why will an N-well
>ring tied to +vdd help? Is vdd meant to be the highest voltage on chip?

Yes.

>
>>> Well! You could hire me and I could sign an NDA ;-)
>
>I can only afford free advice at the moment... :(
>
>Thanks
>qq

Lack of information makes it difficult to give cogent advice.

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>Jim Thompson wrote:
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>> On 3 Jan 2006 08:55:03 -0800, "QQ" <q_q_404@xxxxxxxxxxx> wrote:
>>
>> >>> N+ buried layer _will_ cut the vertical beta, but I wouldn't count on
>> >>> it for safety.
>> >
>> >Could you please explain why does it cut the pnp?
>>
>> Richer doped base _generally_ loses beta, but not always... depends on
>> the other doping levels.
>>
>> >What risk still
>> >exists?
>>
>> Latch-up. If your connection was an absolute necessity you could add
>> an N-well ring around the device tied to +VDD.
>>
>> However I smell that you are using some kind of array where you don't
>> have the latitude afforded by a custom layout??
>>
>> >
>> >>> Can you describe your application in more detail?
>> >
>> >I would like to but cannot because of confidentiality. Hope you will
>> >understand.
>> >
>> >Thanks
>> >qq
>>
>> Well! You could hire me and I could sign an NDA ;-)
>>
>> ...Jim Thompson


...Jim Thompson
--
| James E.Thompson, P.E. | mens |
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