Re: Jitter measurement

On Sat, 21 Jan 2006 16:13:04 +0000 (UTC), kensmith@xxxxxxxxxxxxxxx (Ken Smith)
wrote:

>In article <jj54t1lb6tpk4v0jnk0dj79ef3setu4olp@xxxxxxx>,
>budgie <me@xxxxxxxxxxx> wrote:
>[....]
>>5369 devices, I am leery of making assumptions In that family, M cycles were
>>counted in the high state, and N in the low state, with M<>N. IIRC they also
>>varied M across one output cycle to achieve "proper" division - the 5369EYRN
>>produced 50Hz from a 3.579545 crystal by this form of "fudged" non-integer
>>division.)
>
>Yes, I've done stuff like this to get non-integer frequency ratios. If
>you have reason to believe that this is the sort of thing they have done,
>it may be worthwhile to try to figure out what they have really done.


I don't have any reason to believ they have done this, but I don;'t know exactly
how they derive 10k from the GPS signal so I can't rule it out.

>Does the 10KHz hold steady if you trigger from the 1PPS pulse? If so, you
>will know that the pattern repeats from one second to the next. This will
>help to assure you that there isn't going to be much below 1HZ.

The 1pps edge is synced to the 10kHz, but that really only requires that every
second there are 10,000 cycles on the 10k line - not that the individual cycles
are themselves uniform. Sort of like the way OUR electricity generation
frequency is +/- a certain frequency tolerance, but as midnight approacheth the
frequency is driven to ensure that at midnight the total number of cycles in the
24-hours is correct.

At one stage I wondered about timing each cycle of the 10k reference pulses
using a higher speed clock and period counting, but the gating would need to be
synced to the 10k pulse - and at the end of the day this would only remove the
uncertainty over the "regularity" of the 10k stream.


>You can buy a really good OCXO for a few hundreds of US$.

I *think* the one in the frequency counter is fairly clean and
wobble/jitter-free. Certainly the side-by side (and Lissajou) comparisons on
the CRO with the PLL unit suggest neither has any issues - if either one had a
problem then it would be evident, even though it wouldn't be clear which.

>or:
>
>Assuming you can make three of your PLL circuits, you could use them to
>help look at the noise in the 10KHz etc. (You can use two but it takes
>more work and you have to assume some stuff)
>
>If you lock multiple identical PLL circuits onto the 10KHz, you can see
>the noise they introduce by comparing their outputs. Exactly how to
>compare them, I haven't thought through yet. (See below)
>
>If you set the loop filter in the PLLs to be very slow, you will know that
>they can't track high frequency noise on their inputs. If you have more
>than one, you can see how much high frequency noise they make. By using
>all combinations of the three, you can solve for the noise for each one.
>
>If you compare two with two different bandwidths, you may be able to see
>the noise in the input. (If the PLLs are too noisy you won't be able to
>see it) If you know the noise performance of your PLLs you can solve for
>the noise in the input signal that comes through in the band the two PLLs
>don't share.
>
>Thinking about comparing:
>
>We need a phase detector that has a low noise and a high gain and that
>doesn't have its over-range point near the point where the two edges
>line up.
>
>Assuming we have VCOs running at a multiple, we can make a phase shifted
>signal for use in an XOR type phase detector. I see a problem with this
>because the noise from the power supplies appears on the output of the XOR
>and this could seriously limit the noise floor.
>
>Perhaps a system with some sort of clean tri-stating would work. You only
>enable the output during a short period near the edge.

Comparing is something I have mused over. I can't discern any wobble or jitter
visually on the CRO comparison, but that only means that it is below the
threshold of visual discernment (sic). Similarly, I can't see any signs on the
loop filter output. Neither of these "easy" comparison approaches lets me
quantify, and hence precludes their use in optimising.

This PLL is far different from those of wide(r)-band synthesisers I am more
familar with. It doesn't have a wide acquisition requirement, so the loop
filter can be over-damped and is ultra-slow.

Being an XOR comparator (which obviously has its own contribution to jitter), at
quadrature lock its output (and the filter output to the varicap) is half-rail.
The varicap control line has a switch to select SETUP or OPERATE functions. In
setup, a half-rail divider voltage feed the VCO which is trimmed to 10MHz. This
is just to centre the PLL operation. The 10MHz VCXO has about a 80Hz range from
rail to rail (non-linear of course but we're not trying to generate linear FM/PM
signals) so that's about 16Hz/volt average slope

I don't for a moment accept the premise that what I have to date is perfect, but
maybe I'm trying to go too far with a simple setup. Maybe it IS *good enough*
as a cal source for the workshop.
.

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