Re: Testing Mosfets in Parallel
In article <1138635926.076501.129040@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>,
EdV <ed_vogel@xxxxxxxxxxx> wrote:
> My group has been tasked with designing a test for a board that
> has ten mosfets in parallel. No jumpering allowed. The
> designers say that adding jumpers and bus bars make the circuit
> oscillate.
> The first thing I want to test is that all of the parts are
> actually stuffed with the correct part(this sort of stuff happens
> to us). Perhaps driving the mosfets into the linear region with a
> modest load and then measuring their individual temperatures with
> an array of thermistors.
They may have directly paralleled all drains and
sources, but at least they should have driven each
gate via separate gate resistors. If so that is
your possible entry point for testing.
Think about dropping the pcb onto a bed of nails,
two nails per device, where you can selectively
short the gate-source of 9 devices, leaving just
one device active for measurement.
Have a 0-12V ADC into a linear gate-driver with
several amps capability, (in order to drive those
9 shorted gate resistors). To avoid dissipation
problems in those resistors, each active gate-
-driving test must only last a few milliseconds.
An 8-bit ADC, clocked at 10KHz, will ramp from
0-12V in 26mS, with 50mV steps. Have a safety
circuit that toggles the drive OFF if the gate
drive is ON for too long (ADC stalled).
Use a 5V/10A dc supply, through a 0.5 ohm
resistor to the commoned drains. May be useful
to have a few selectable values of resistor.
Dual-beam scope needed, probing Vgs and Vds.
An IEEE scope will enable data to be snatched
off quickly.
Do three broad tests.
1) All devices OFF. Check that Vds = Vsupply.
You may change the 0.5 ohm for a higher value
for this test. This is the leakage current test.
2) Pulse 12V Vgs to one device, measure Vds at 10A.
This is the ON resistance test.
3) Ramp the Vgs of one device 0-12V, plot Vds at the
same time. This characterises Id versus Vgs, or
gets Vgs(threshold).
It all hangs on whether they used separate gate
resistors and what value.............
--
Tony Williams.
.
Relevant Pages
- Re: Biasing of Dual Gate Fets
... Say I have an RF chock in the Drain then Vds is almost 8V. ... setting up bias for a Dual Gate MOSFET. ... There should be a graph that shows the operating characteristic curves. ... characteristic curves will be for various levels of Vgs. ...
(rec.radio.amateur.homebrew) - Re: Q to Win re:oscillation in high-voltage MOSFETS
... > This "model" appears to work with low gate resistance values, ... Motorola's AN1043, pub 1989), adopted by Fairchild and others, ... The Motorola approach turns on two small "INTER" FETs instead, ... Motorola included two 10meg resistors in parallel with the ...
(sci.electronics.design) - Re: small inverter driver chip
... It uses two caps, two resistors, ... one diode, two ic's, and provides a symmetrical duty cycle with adjustable ... When the gate output goes low, turn on that side of the bridge. ...
(sci.electronics.design) - Re: Q to Win re:oscillation in high-voltage MOSFETS
... >> Back to the Motorola approach. ... >> Motorola included two 10meg resistors in parallel with the ... >> gate current you complained about. ...
(sci.electronics.design) - Re: Testing Mosfets in Parallel
... >> My group has been tasked with designing a test for a board that ... >> has ten mosfets in parallel. ... > gate via separate gate resistors. ...
(sci.electronics.design) |
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