Re: Hans Camenzind's Book, Designing Analog Chips

Joerg wrote:

Hello Jim,


Naaah. A MOSIS run is quite cheap. Each process has a "shuttle"
run... multiple chip designs on a single wafer. Good cheap way for
"proof of pudding".


The run isn't so expensive but there you have to do the full chip design
from scratch. I know that this is your bread and butter but many times
my clients shy away from that because of the design costs. If it were
just one or two metal mask layouts it might be easier to convince them.

I reckon the layout would be much easier if you use MOSIS since then you are
not stuck with the component placement you get, you are free to move stuff.
Also you'll get several real metal layers so you don't have to mess around
with resistive cross-unders. If ESD performance is very important to you
then you might need to ask someone experienced to show you how to do ESD
cells for the IO pads, but the rest of the chip should be quite simulatable
and predictable. You'd need some decent models which I think you would get
under NDA with MOSIS, and you'd need some software too.



And I might add... he who complains about resistor values shouldn't be
trying to design an I/C ;-)


Well, I am not complaining about tolerances since you can do ratios.
It's ok if they are 30% or whatever but low power designs require at
least one type in the 1M range. Dividers for low battery detect, other
thresholds and so on. Can't do current sources everywhere, plus they eat
from the rather small pool of NPN/PNP.
More reason to go MOSIS. You need to think about the total resistance in
your circuit, so having one 1M resistor is a reasonable proposition, but
asking for 20 of them is being greedy since for high value resistors
(minimum width), the chip area is proportional to the resistance value.

Chris
.