Re: Digital Osci and Logic Analyzer

Rich Webb <bbew.ar@xxxxxxxxxxxxxxxxxx> wrote:

On Fri, 7 Apr 2006 02:43:39 -0500, "Abstract Dissonance"
<Abstract.Dissonance@xxxxxxxxxxx> wrote:

How complicated is it to create a simple pc based oscilloscope and logic
analyzer(excluding the pc software)?

Does it just consist of getting a ADC and interface for sending the data to
the pc? I'm looking at trying to make one in a similar way to what is done
on this site:

http://www.fpga4fun.com/digitalscope.html

I figured that the main the parts are the ADC, the probe, and the method of
sending the information(which I think is the hardest part at high data
rates?)? I've seen some ADC's that have sample rates of over 100Msps which
should give me a 50Mhz bandwidth? Although these aren't cheep I've also
seen some upwards of 1Gsps that would give me a larger bandwidth if I needed
it.

As a rule of thumb, estimate the useable bandwidth as being limited by
one-tenth of the ADC sample rate, not one-half. That lets you recover
(more or less) the fifth harmonic of the signal of interest right at
Nyquist. For some commercial examples, there's the Fluke 199C: 2.5 Gsps,
overall bandwidth 200 MHz; and Tek TDS2012: 1 Gsps and 100 MHz. So for
your

I disagree here. Shannon says a signal can be reconstructed up to half
the sampling frequency. The higher sampling rates of the examples you
mention are probably used to use less bits for sampling and make the
analog input filter easier to construct (an RC filter still won't do
the job) to prevent frequency aliasing. Digital filtering does the
rest.

Lets suppose I decide to buy a 1Gsps ADC(which isn't going to happen any
time soon) and I have a probe that works properly with the ADC. How would I
go about storing/streaming all those samples? This would require a memory
chip be able to work down at 1ns or so? I was thinking I could use several
gigs of pc memory in parallel to reduce the latency and increase total
sample size to a few seconds... is this possible? What about encoding for a
digital stream? do something like rle on the bit stream where 01 one would
store 2 bits as one and its number of repetitions? (need to use 2 bits
atleast so things like a clock signal are encoded efficiently)

You don't need to capture or store more samples than you need for one
display screen.

Assume that your display area is 500 pixels x 500 pixels at ten
divisions each for horizontal and vertical. No matter how fast you
sample, you've only that area to work with. For each time step (vertical
column) you have several choices.

I disagree again, the less memory you have the more difficult it will
be to capture a problem. You'll need some pretty fancy triggering.

You can decimate your sample rate down to where you grab just one
instantaneous sample at that tick and store/plot only that value. For
example, at 1 msec/div and 50 pixels/div that's just 500 samples at a
lazy 50 Ksps rate.

Which makes the oscilloscope totally useless to capture problems. A
good DSO can store loads of samples which where sampled at the highest
possible frequency.

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