ADC "stacking"
is it possible to run ADC's in parallel to get increased sample rate?
I.e.
Signal ----+--> ADC1 ------------>
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+-- Delay --> ADC2 --->
so each ADC runs, lets say, at M mhz and Delay is a delay of 1/(2*M)
seconds. So in a sense ADC2 samples "inbetween" what ADC1 samples. This
would effectively increase the sampling rate by 2? I'm sure that the delay
would have to be designed almost perfectly so that no distortion would arise
because the samples would be expected to be equally spaced?
Thanks,
Jon
.
Relevant Pages
- Re: Sudden B+
... incorporating this type of design with high voltages is somewhat ... a tube diode can be used to delay the B+. ... Jon is an idiot and a sockpuppet of Weicked. ... off and on again renders the thermal relay unreliable with possible negative ...
(rec.audio.tubes) - Re: Propagation delay sensitivity to temperature, voltage, and manufacturing
... First I have to warn you about using a DCM output as ADC clock. ... DCM output has significant jitter, which costs you dearly in raising ... Regarding the more benevolent aspect of delay change: ... with temperature. ...
(comp.arch.fpga) - Re: anti-aliasing
... ballpark 12 KHz in this case, and the input to the adc was a sine wave ... The adc will take a bunch of samples, ... So maybe I can fuzz up the sample rate so that it can't alias against ... I could add a pseudo-random delay after every adc sample shot; ...
(sci.electronics.design) - Re: anti-aliasing
... ballpark 12 KHz in this case, and the input to the adc was a sine wave ... The adc will take a bunch of samples, ... So maybe I can fuzz up the sample rate so that it can't alias against ... I could add a pseudo-random delay after every adc sample shot; ...
(sci.electronics.design) - Re: Col view directory not smart enough?
... see_signature@xxxxxxxxxxxxxxx (Jon) wrote: ... Does this sound like something that could be acceptable to others as ... Option key while pausing over a "too long" name, you avoid the delay. ...
(comp.sys.mac.apps) |
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