Re: ADC "stacking"
- From: Ben Bradley <ben_nospam_bradley@xxxxxxxxxxxxxxx>
- Date: Mon, 10 Apr 2006 06:08:12 GMT
On Fri, 7 Apr 2006 16:22:10 -0500, "Abstract Dissonance"
<Abstract.Dissonance@xxxxxxxxxxx> wrote:
is it possible to run ADC's in parallel to get increased sample rate?
Interesting thread (I've read it all). I recall about eight years
ago, a coworker was working on a digital RF receiver with a bandwidth
of around maybe 50 to 70 MHZ. recall discussing the idea of using the
ADC chips interleaved for higher bandwidth, and also that the data
sheet saying interleaved used was not recommended (I don't remember
the A/D chip used), but it didn't say why. Would anyone know why it
would say this, other than the diffuculties already discussed in this
thread?
I.e.
Signal ----+--> ADC1 ------------>
|
+-- Delay --> ADC2 --->
so each ADC runs, lets say, at M mhz and Delay is a delay of 1/(2*M)
seconds. So in a sense ADC2 samples "inbetween" what ADC1 samples. This
would effectively increase the sampling rate by 2? I'm sure that the delay
would have to be designed almost perfectly so that no distortion would arise
because the samples would be expected to be equally spaced?
Thanks,
Jon
.
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