safe logic

Hello,

I am looking for designs for inherent failsafe logic gates using
transistors and relais, i.e. gates that fail safely if any component
fails.

An example for an AND would be two cascaded common emitter stages, the
inputs applied to the collectors while the base of the first transistor
is excited with a square wave. If any of the transistors fails the
output will not be AC and therefore blocked by the transformer.

Input A Input B

| |
.-. .-.
| | | |
| | | |
'-' '-'
| ------------. ,-->|- Output
| | )|(
|------- | )|( A AND B
| | | -' '-
| | | | |
___ |/ | |/ === ===
-|___|----| \---| GND GND
|> |>
square | |
clock | |
=== ===
GND GND
(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)



Any article/book recommendations on this topic?


Many thanks!


Daniel

.