Re: pulse delay circuit

Discrete solution. With better R values the R-S f/f can be two transistor.
Add another if you want a pulse after a delay rater than just a delay.

http://webpages.charter.net/dawill/Images/One-shot%20Timer.gif

Timing should be consistent enough (with respect to R and C) without
adjustments (as opposed to, say, CMOS threshold variation).

Tim

--
Deep Fryer: a very philosophical monk.
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"Mark Kelepouris" <markkelepouris@xxxxxxxxxxxxxxx> wrote in message
news:448a9309$0$14243$afc38c87@xxxxxxxxxxxxxxxxxxxxxxx
Hello to all,
I'm in need of a simple delay circuit for the positive edge of a pulse of
12 VDC.
I need to create a delayed version of about 20 uS and it must be realiable
and within a couple of uS tolerance.
I am planning to use the 74HC123 dual oneshot for the delay control but
i'm not sure how best to translate 12 volts down to 5 and back up to 12
again at the output without any unrealiablities adding to the circuit.
I'm guessing two tranny's and four resistors would be a bare minimum, but
i'm not sure which transistors i need to use and how best to bias and
supply voltage/current to them for the desired results. (12>5Vdc..20uS
delay..5>12Vdc)
Can anyone offer advice on this?

Thanks,
Mark Kelepouris



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